ArmPkg: update RVCT assembly functions to use new RVCT_ASM_EXPORT macro

[mirror_edk2.git] / ArmPkg / Library / ArmLib / Common / Arm / ArmLibSupport.asm

diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
index 9e6d57ef6f45bac94d40d13f37077a224769777f..bdd862a96acb836065a3e78a92b4bdf364887dc1 100644 (file)
--- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
+++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
@@ -1,4 +1,4 @@
-//------------------------------------------------------------------------------ \r
+//------------------------------------------------------------------------------\r
 //\r
 // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
 // Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
@@ -14,71 +14,39 @@
 //------------------------------------------------------------------------------\r
 \r
 #include <AsmMacroIoLib.h>\r
-    \r
+\r
     INCLUDE AsmMacroIoLib.inc\r
 \r
-#ifdef ARM_CPU_ARMv6\r
-// No memory barriers for ARMv6\r
-#define isb\r
-#define dsb\r
-#endif\r
-\r
-    EXPORT ArmReadMidr\r
-    EXPORT ArmCacheInfo\r
-    EXPORT ArmGetInterruptState\r
-    EXPORT ArmGetFiqState\r
-    EXPORT ArmGetTTBR0BaseAddress\r
-    EXPORT ArmSetTTBR0\r
-    EXPORT ArmSetDomainAccessControl\r
-    EXPORT CPSRMaskInsert\r
-    EXPORT CPSRRead\r
-    EXPORT ArmReadCpacr\r
-    EXPORT ArmWriteCpacr\r
-    EXPORT ArmWriteAuxCr\r
-    EXPORT ArmReadAuxCr\r
-    EXPORT ArmInvalidateTlb\r
-    EXPORT ArmUpdateTranslationTableEntry\r
-    EXPORT ArmReadScr\r
-    EXPORT ArmWriteScr\r
-    EXPORT ArmReadMVBar\r
-    EXPORT ArmWriteMVBar\r
-    EXPORT ArmReadHVBar\r
-    EXPORT ArmWriteHVBar\r
-    EXPORT ArmCallWFE\r
-    EXPORT ArmCallSEV\r
-    EXPORT ArmReadSctlr\r
-    EXPORT ArmReadCpuActlr\r
-    EXPORT ArmWriteCpuActlr\r
-\r
-    AREA ArmLibSupport, CODE, READONLY\r
-\r
-ArmReadMidr\r
+\r
+    INCLUDE AsmMacroExport.inc\r
+\r
+ RVCT_ASM_EXPORT ArmReadMidr\r
   mrc     p15,0,R0,c0,c0,0\r
   bx      LR\r
 \r
-ArmCacheInfo\r
+ RVCT_ASM_EXPORT ArmCacheInfo\r
   mrc     p15,0,R0,c0,c0,1\r
   bx      LR\r
 \r
-ArmGetInterruptState\r
+ RVCT_ASM_EXPORT ArmGetInterruptState\r
   mrs     R0,CPSR\r
   tst     R0,#0x80      // Check if IRQ is enabled.\r
   moveq   R0,#1\r
   movne   R0,#0\r
   bx      LR\r
 \r
-ArmGetFiqState\r
+ RVCT_ASM_EXPORT ArmGetFiqState\r
   mrs     R0,CPSR\r
   tst     R0,#0x40      // Check if FIQ is enabled.\r
   moveq   R0,#1\r
   movne   R0,#0\r
   bx      LR\r
 \r
-ArmSetDomainAccessControl\r
+ RVCT_ASM_EXPORT ArmSetDomainAccessControl\r
   mcr     p15,0,r0,c3,c0,0\r
   bx      lr\r
 \r
-CPSRMaskInsert    // on entry, r0 is the mask and r1 is the field to insert\r
+ RVCT_ASM_EXPORT CPSRMaskInsert\r
   stmfd   sp!, {r4-r12, lr} // save all the banked registers\r
   mov     r3, sp            // copy the stack pointer into a non-banked register\r
   mrs     r2, cpsr          // read the cpsr\r
@@ -91,33 +59,33 @@ CPSRMaskInsert    // on entry, r0 is the mask and r1 is the field to insert
   ldmfd   sp!, {r4-r12, lr} // restore registers\r
   bx      lr                // return (hopefully thumb-safe!)             // return (hopefully thumb-safe!)\r
 \r
-CPSRRead\r
+ RVCT_ASM_EXPORT CPSRRead\r
   mrs     r0, cpsr\r
   bx      lr\r
 \r
-ArmReadCpacr\r
+ RVCT_ASM_EXPORT ArmReadCpacr\r
   mrc     p15, 0, r0, c1, c0, 2\r
   bx      lr\r
 \r
-ArmWriteCpacr\r
+ RVCT_ASM_EXPORT ArmWriteCpacr\r
   mcr     p15, 0, r0, c1, c0, 2\r
   isb\r
   bx      lr\r
 \r
-ArmWriteAuxCr\r
+ RVCT_ASM_EXPORT ArmWriteAuxCr\r
   mcr     p15, 0, r0, c1, c0, 1\r
   bx      lr\r
 \r
-ArmReadAuxCr\r
+ RVCT_ASM_EXPORT ArmReadAuxCr\r
   mrc     p15, 0, r0, c1, c0, 1\r
-  bx      lr  \r
+  bx      lr\r
 \r
-ArmSetTTBR0\r
+ RVCT_ASM_EXPORT ArmSetTTBR0\r
   mcr     p15,0,r0,c2,c0,0\r
   isb\r
   bx      lr\r
 \r
-ArmGetTTBR0BaseAddress\r
+ RVCT_ASM_EXPORT ArmGetTTBR0BaseAddress\r
   mrc     p15,0,r0,c2,c0,0\r
   LoadConstantToReg(0xFFFFC000, r1)\r
   and     r0, r0, r1\r
@@ -130,7 +98,7 @@ ArmGetTTBR0BaseAddress
 //  IN VOID  *TranslationTableEntry  // R0\r
 //  IN VOID  *MVA                    // R1\r
 //  );\r
-ArmUpdateTranslationTableEntry\r
+ RVCT_ASM_EXPORT ArmUpdateTranslationTableEntry\r
   mcr     p15,0,R0,c7,c14,1     // DCCIMVAC Clean data cache by MVA\r
   dsb\r
   mcr     p15,0,R1,c8,c7,1      // TLBIMVA TLB Invalidate MVA\r
@@ -139,7 +107,7 @@ ArmUpdateTranslationTableEntry
   isb\r
   bx      lr\r
 \r
-ArmInvalidateTlb\r
+ RVCT_ASM_EXPORT ArmInvalidateTlb\r
   mov     r0,#0\r
   mcr     p15,0,r0,c8,c7,0\r
   mcr     p15,0,R9,c7,c5,6      // BPIALL Invalidate Branch predictor array. R9 == NoOp\r
@@ -147,48 +115,48 @@ ArmInvalidateTlb
   isb\r
   bx      lr\r
 \r
-ArmReadScr\r
+ RVCT_ASM_EXPORT ArmReadScr\r
   mrc     p15, 0, r0, c1, c1, 0\r
   bx      lr\r
 \r
-ArmWriteScr\r
+ RVCT_ASM_EXPORT ArmWriteScr\r
   mcr     p15, 0, r0, c1, c1, 0\r
   bx      lr\r
 \r
-ArmReadHVBar\r
+ RVCT_ASM_EXPORT ArmReadHVBar\r
   mrc     p15, 4, r0, c12, c0, 0\r
   bx      lr\r
 \r
-ArmWriteHVBar\r
+ RVCT_ASM_EXPORT ArmWriteHVBar\r
   mcr     p15, 4, r0, c12, c0, 0\r
   bx      lr\r
 \r
-ArmReadMVBar\r
+ RVCT_ASM_EXPORT ArmReadMVBar\r
   mrc     p15, 0, r0, c12, c0, 1\r
   bx      lr\r
 \r
-ArmWriteMVBar\r
+ RVCT_ASM_EXPORT ArmWriteMVBar\r
   mcr     p15, 0, r0, c12, c0, 1\r
   bx      lr\r
-  \r
-ArmCallWFE\r
+\r
+ RVCT_ASM_EXPORT ArmCallWFE\r
   wfe\r
   bx      lr\r
 \r
-ArmCallSEV\r
+ RVCT_ASM_EXPORT ArmCallSEV\r
   sev\r
   bx      lr\r
 \r
-ArmReadSctlr\r
+ RVCT_ASM_EXPORT ArmReadSctlr\r
   mrc     p15, 0, r0, c1, c0, 0      // Read SCTLR into R0 (Read control register configuration data)\r
-  bx     lr\r
+  bx      lr\r
 \r
 \r
-ArmReadCpuActlr\r
+ RVCT_ASM_EXPORT ArmReadCpuActlr\r
   mrc     p15, 0, r0, c1, c0, 1\r
   bx      lr\r
 \r
-ArmWriteCpuActlr\r
+ RVCT_ASM_EXPORT ArmWriteCpuActlr\r
   mcr     p15, 0, r0, c1, c0, 1\r
   dsb\r
   isb\r