Fixes to get CodeSourcery GCC and RVCT 3.1 compiling.

[mirror_edk2.git] / ArmPkg / Library / ArmLib / Common / ArmLibSupport.S

diff --git a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S
index c644d3446e9a9fa374d57df2ea3dbf76ad2e6415..29ccf6dcebba6dfcb5eeac509319ae89fa745960 100644 (file)
--- a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S
@@ -1,8 +1,8 @@
 #------------------------------------------------------------------------------ 
 #
-# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
 #
-# All rights reserved. This program and the accompanying materials
+# This program and the accompanying materials
 # are licensed and made available under the terms and conditions of the BSD License
 # which accompanies this distribution.  The full text of the license may be found at
 # http://opensource.org/licenses/bsd-license.php
@@ -12,22 +12,24 @@
 #
 #------------------------------------------------------------------------------
 
+#include <AsmMacroIoLib.h>
+
 .text
 .align 2
-.globl ASM_PFX(Cp15IdCode)
-.globl ASM_PFX(Cp15CacheInfo)
-.globl ASM_PFX(ArmEnableInterrupts)
-.globl ASM_PFX(ArmDisableInterrupts)
-.globl ASM_PFX(ArmGetInterruptState)
-.globl ASM_PFX(ArmEnableFiq)
-.globl ASM_PFX(ArmDisableFiq)
-.globl ASM_PFX(ArmGetFiqState)
-.globl ASM_PFX(ArmInvalidateTlb)
-.globl ASM_PFX(ArmSetTranslationTableBaseAddress)
-.globl ASM_PFX(ArmGetTranslationTableBaseAddress)
-.globl ASM_PFX(ArmSetDomainAccessControl)
-.globl ASM_PFX(CPSRMaskInsert)
-.globl ASM_PFX(CPSRRead)
+GCC_ASM_EXPORT(Cp15IdCode)
+GCC_ASM_EXPORT(Cp15CacheInfo)
+GCC_ASM_EXPORT(ArmEnableInterrupts)
+GCC_ASM_EXPORT(ArmDisableInterrupts)
+GCC_ASM_EXPORT(ArmGetInterruptState)
+GCC_ASM_EXPORT(ArmEnableFiq)
+GCC_ASM_EXPORT(ArmDisableFiq)
+GCC_ASM_EXPORT(ArmGetFiqState)
+GCC_ASM_EXPORT(ArmInvalidateTlb)
+GCC_ASM_EXPORT(ArmSetTTBR0)
+GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)
+GCC_ASM_EXPORT(ArmSetDomainAccessControl)
+GCC_ASM_EXPORT(CPSRMaskInsert)
+GCC_ASM_EXPORT(CPSRRead)
 
 #------------------------------------------------------------------------------
 
@@ -40,60 +42,62 @@ ASM_PFX(Cp15CacheInfo):
   bx      LR
 
 ASM_PFX(ArmEnableInterrupts):
-       mrs     R0,CPSR
-       bic     R0,R0,#0x80             @Enable IRQ interrupts
-       msr     CPSR_c,R0
-       bx      LR
+  mrs     R0,CPSR
+  bic     R0,R0,#0x80    @Enable IRQ interrupts
+  msr     CPSR_c,R0
+  bx      LR
 
 ASM_PFX(ArmDisableInterrupts):
-       mrs     R0,CPSR
-       orr     R1,R0,#0x80             @Disable IRQ interrupts
-       msr     CPSR_c,R1
+  mrs     R0,CPSR
+  orr     R1,R0,#0x80    @Disable IRQ interrupts
+  msr     CPSR_c,R1
   tst     R0,#0x80
   moveq   R0,#1
   movne   R0,#0
-       bx      LR
+  bx      LR
 
 ASM_PFX(ArmGetInterruptState):
-       mrs     R0,CPSR
-       tst     R0,#0x80            @Check if IRQ is enabled.
-       moveq   R0,#1
-       movne   R0,#0
-       bx      LR
+  mrs     R0,CPSR
+  tst     R0,#0x80      @Check if IRQ is enabled.
+  moveq   R0,#1
+  movne   R0,#0
+  bx      LR
 
 ASM_PFX(ArmEnableFiq):
-       mrs     R0,CPSR
-       bic     R0,R0,#0x40             @Enable FIQ interrupts
-       msr     CPSR_c,R0
-       bx      LR
+  mrs     R0,CPSR
+  bic     R0,R0,#0x40    @Enable FIQ interrupts
+  msr     CPSR_c,R0
+  bx      LR
 
 ASM_PFX(ArmDisableFiq):
-       mrs     R0,CPSR
-       orr     R1,R0,#0x40             @Disable FIQ interrupts
-       msr     CPSR_c,R1
+  mrs     R0,CPSR
+  orr     R1,R0,#0x40    @Disable FIQ interrupts
+  msr     CPSR_c,R1
   tst     R0,#0x80
   moveq   R0,#1
   movne   R0,#0
-       bx      LR
+  bx      LR
 
 ASM_PFX(ArmGetFiqState):
-       mrs     R0,CPSR
-       tst     R0,#0x80            @Check if FIQ is enabled.
-       moveq   R0,#1
-       movne   R0,#0
-       bx      LR
+  mrs     R0,CPSR
+  tst     R0,#0x80      @Check if FIQ is enabled.
+  moveq   R0,#1
+  movne   R0,#0
+  bx      LR
 
 ASM_PFX(ArmInvalidateTlb):
   mov     r0,#0
   mcr     p15,0,r0,c8,c7,0
   bx      lr
 
-ASM_PFX(ArmSetTranslationTableBaseAddress):
+ASM_PFX(ArmSetTTBR0):
   mcr     p15,0,r0,c2,c0,0
   bx      lr
 
-ASM_PFX(ArmGetTranslationTableBaseAddress):
+ASM_PFX(ArmGetTTBR0BaseAddress):
   mrc     p15,0,r0,c2,c0,0
+  LoadConstantToReg(0xFFFFC000, r1)   @  and     r0, r0, #0xFFFFC000
+  and     r0, r0, r1
   bx      lr