Sync up ArmPkg with patch from mailing list. Changed name of BdsLib.h to BdsUnixLib...

[mirror_edk2.git] / ArmPkg / Library / ArmLib / Common / ArmLibSupport.S

diff --git a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S
index e5e9b54fc2c9ed5c5db826dc54c1ebd5ae004594..9b144c82c5918fb4d2ea720936d63f7f097f3812 100644 (file)
--- a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S
@@ -12,22 +12,24 @@
 #
 #------------------------------------------------------------------------------
 
+#include <AsmMacroIoLib.h>
+
 .text
 .align 2
-.globl ASM_PFX(Cp15IdCode)
-.globl ASM_PFX(Cp15CacheInfo)
-.globl ASM_PFX(ArmEnableInterrupts)
-.globl ASM_PFX(ArmDisableInterrupts)
-.globl ASM_PFX(ArmGetInterruptState)
-.globl ASM_PFX(ArmEnableFiq)
-.globl ASM_PFX(ArmDisableFiq)
-.globl ASM_PFX(ArmGetFiqState)
-.globl ASM_PFX(ArmInvalidateTlb)
-.globl ASM_PFX(ArmSetTranslationTableBaseAddress)
-.globl ASM_PFX(ArmGetTranslationTableBaseAddress)
-.globl ASM_PFX(ArmSetDomainAccessControl)
-.globl ASM_PFX(CPSRMaskInsert)
-.globl ASM_PFX(CPSRRead)
+GCC_ASM_EXPORT(Cp15IdCode)
+GCC_ASM_EXPORT(Cp15CacheInfo)
+GCC_ASM_EXPORT(ArmEnableInterrupts)
+GCC_ASM_EXPORT(ArmDisableInterrupts)
+GCC_ASM_EXPORT(ArmGetInterruptState)
+GCC_ASM_EXPORT(ArmEnableFiq)
+GCC_ASM_EXPORT(ArmDisableFiq)
+GCC_ASM_EXPORT(ArmGetFiqState)
+GCC_ASM_EXPORT(ArmInvalidateTlb)
+GCC_ASM_EXPORT(ArmSetTTBR0)
+GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)
+GCC_ASM_EXPORT(ArmSetDomainAccessControl)
+GCC_ASM_EXPORT(CPSRMaskInsert)
+GCC_ASM_EXPORT(CPSRRead)
 
 #------------------------------------------------------------------------------
 
@@ -88,12 +90,14 @@ ASM_PFX(ArmInvalidateTlb):
   mcr     p15,0,r0,c8,c7,0
   bx      lr
 
-ASM_PFX(ArmSetTranslationTableBaseAddress):
+ASM_PFX(ArmSetTTBR0):
   mcr     p15,0,r0,c2,c0,0
   bx      lr
 
-ASM_PFX(ArmGetTranslationTableBaseAddress):
+ASM_PFX(ArmGetTTBR0BaseAddress):
   mrc     p15,0,r0,c2,c0,0
+  LoadConstantToReg(0xFFFFC000, r1)   @  and     r0, r0, #0xFFFFC000
+  and     r0, r0, r1
   bx      lr