-#------------------------------------------------------------------------------
-#
-# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
-
-#include <AsmMacroIoLib.h>
-
-.text
-.align 2
-GCC_ASM_EXPORT(Cp15IdCode)
-GCC_ASM_EXPORT(Cp15CacheInfo)
-GCC_ASM_EXPORT(ArmEnableInterrupts)
-GCC_ASM_EXPORT(ArmDisableInterrupts)
-GCC_ASM_EXPORT(ArmGetInterruptState)
-GCC_ASM_EXPORT(ArmEnableFiq)
-GCC_ASM_EXPORT(ArmDisableFiq)
-GCC_ASM_EXPORT(ArmGetFiqState)
-GCC_ASM_EXPORT(ArmInvalidateTlb)
-GCC_ASM_EXPORT(ArmSetTTBR0)
-GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)
-GCC_ASM_EXPORT(ArmSetDomainAccessControl)
-GCC_ASM_EXPORT(CPSRMaskInsert)
-GCC_ASM_EXPORT(CPSRRead)
-
-#------------------------------------------------------------------------------
-
-ASM_PFX(Cp15IdCode):
- mrc p15,0,R0,c0,c0,0
- bx LR
-
-ASM_PFX(Cp15CacheInfo):
- mrc p15,0,R0,c0,c0,1
- bx LR
-
-ASM_PFX(ArmEnableInterrupts):
-\s\smrs R0,CPSR
-\s\sbic R0,R0,#0x80\s\s\s\s@Enable IRQ interrupts
-\s\smsr CPSR_c,R0
-\s\sbx LR
-
-ASM_PFX(ArmDisableInterrupts):
-\s\smrs R0,CPSR
-\s\sorr R1,R0,#0x80\s\s\s\s@Disable IRQ interrupts
-\s\smsr CPSR_c,R1
- tst R0,#0x80
- moveq R0,#1
- movne R0,#0
-\s\sbx LR
-
-ASM_PFX(ArmGetInterruptState):
-\s\smrs R0,CPSR
-\s\stst R0,#0x80\s\s @Check if IRQ is enabled.
-\s\smoveq R0,#1
-\s\smovne R0,#0
-\s\sbx LR
-
-ASM_PFX(ArmEnableFiq):
-\s\smrs R0,CPSR
-\s\sbic R0,R0,#0x40\s\s\s\s@Enable FIQ interrupts
-\s\smsr CPSR_c,R0
-\s\sbx LR
-
-ASM_PFX(ArmDisableFiq):
-\s\smrs R0,CPSR
-\s\sorr R1,R0,#0x40\s\s\s\s@Disable FIQ interrupts
-\s\smsr CPSR_c,R1
- tst R0,#0x80
- moveq R0,#1
- movne R0,#0
-\s\sbx LR
-
-ASM_PFX(ArmGetFiqState):
-\s\smrs R0,CPSR
-\s\stst R0,#0x80\s\s @Check if FIQ is enabled.
-\s\smoveq R0,#1
-\s\smovne R0,#0
-\s\sbx LR
-
-ASM_PFX(ArmInvalidateTlb):
- mov r0,#0
- mcr p15,0,r0,c8,c7,0
- bx lr
-
-ASM_PFX(ArmSetTTBR0):
- mcr p15,0,r0,c2,c0,0
- bx lr
-
-ASM_PFX(ArmGetTTBR0BaseAddress):
- mrc p15,0,r0,c2,c0,0
- LoadConstantToReg(0xFFFFC000, r1) @ and r0, r0, #0xFFFFC000
- and r0, r0, r1
- bx lr
-
-
-ASM_PFX(ArmSetDomainAccessControl):
- mcr p15,0,r0,c3,c0,0
- bx lr
-
-ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert
- stmfd sp!, {r4-r12, lr} @ save all the banked registers
- mov r3, sp @ copy the stack pointer into a non-banked register
- mrs r2, cpsr @ read the cpsr
- bic r2, r2, r0 @ clear mask in the cpsr
- and r1, r1, r0 @ clear bits outside the mask in the input
- orr r2, r2, r1 @ set field
- msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)
- mov sp, r3 @ restore stack pointer
- ldmfd sp!, {r4-r12, lr} @ restore registers
- bx lr @ return (hopefully thumb-safe!)
-
-ASM_PFX(CPSRRead):
- mrs r0, cpsr
- bx lr
-
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED
+#------------------------------------------------------------------------------ \r
+#\r
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#include <AsmMacroIoLib.h>\r
+\r
+#ifdef ARM_CPU_ARMv6\r
+// No memory barriers for ARMv6\r
+#define isb\r
+#define dsb\r
+#endif\r
+\r
+.text\r
+.align 2\r
+GCC_ASM_EXPORT(Cp15IdCode)\r
+GCC_ASM_EXPORT(Cp15CacheInfo)\r
+GCC_ASM_EXPORT(ArmGetInterruptState)\r
+GCC_ASM_EXPORT(ArmGetFiqState)\r
+GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)\r
+GCC_ASM_EXPORT(ArmSetTTBR0)\r
+GCC_ASM_EXPORT(ArmSetDomainAccessControl)\r
+GCC_ASM_EXPORT(CPSRMaskInsert)\r
+GCC_ASM_EXPORT(CPSRRead)\r
+GCC_ASM_EXPORT(ArmReadCpacr)\r
+GCC_ASM_EXPORT(ArmWriteCpacr)\r
+GCC_ASM_EXPORT(ArmWriteAuxCr)\r
+GCC_ASM_EXPORT(ArmReadAuxCr)\r
+GCC_ASM_EXPORT(ArmInvalidateTlb)\r
+GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)\r
+GCC_ASM_EXPORT(ArmReadNsacr)\r
+GCC_ASM_EXPORT(ArmWriteNsacr)\r
+GCC_ASM_EXPORT(ArmReadScr)\r
+GCC_ASM_EXPORT(ArmWriteScr)\r
+GCC_ASM_EXPORT(ArmReadMVBar)\r
+GCC_ASM_EXPORT(ArmWriteMVBar)\r
+GCC_ASM_EXPORT(ArmCallWFE)\r
+GCC_ASM_EXPORT(ArmCallSEV)\r
+GCC_ASM_EXPORT(ArmReadSctlr)\r
+\r
+#------------------------------------------------------------------------------\r
+\r
+ASM_PFX(Cp15IdCode):\r
+ mrc p15,0,R0,c0,c0,0\r
+ bx LR\r
+\r
+ASM_PFX(Cp15CacheInfo):\r
+ mrc p15,0,R0,c0,c0,1\r
+ bx LR\r
+\r
+ASM_PFX(ArmGetInterruptState):\r
+ mrs R0,CPSR\r
+ tst R0,#0x80 @Check if IRQ is enabled.\r
+ moveq R0,#1\r
+ movne R0,#0\r
+ bx LR\r
+\r
+ASM_PFX(ArmGetFiqState):\r
+ mrs R0,CPSR\r
+ tst R0,#0x40 @Check if FIQ is enabled.\r
+ moveq R0,#1\r
+ movne R0,#0\r
+ bx LR\r
+\r
+ASM_PFX(ArmSetDomainAccessControl):\r
+ mcr p15,0,r0,c3,c0,0\r
+ bx lr\r
+\r
+ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert\r
+ stmfd sp!, {r4-r12, lr} @ save all the banked registers\r
+ mov r3, sp @ copy the stack pointer into a non-banked register\r
+ mrs r2, cpsr @ read the cpsr\r
+ bic r2, r2, r0 @ clear mask in the cpsr\r
+ and r1, r1, r0 @ clear bits outside the mask in the input\r
+ orr r2, r2, r1 @ set field\r
+ msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)\r
+ isb\r
+ mov sp, r3 @ restore stack pointer\r
+ ldmfd sp!, {r4-r12, lr} @ restore registers\r
+ bx lr @ return (hopefully thumb-safe!) @ return (hopefully thumb-safe!)\r
+\r
+ASM_PFX(CPSRRead):\r
+ mrs r0, cpsr\r
+ bx lr\r
+\r
+ASM_PFX(ArmReadCpacr):\r
+ mrc p15, 0, r0, c1, c0, 2\r
+ bx lr\r
+\r
+ASM_PFX(ArmWriteCpacr):\r
+ mcr p15, 0, r0, c1, c0, 2\r
+ isb\r
+ bx lr\r
+\r
+ASM_PFX(ArmWriteAuxCr):\r
+ mcr p15, 0, r0, c1, c0, 1\r
+ bx lr\r
+\r
+ASM_PFX(ArmReadAuxCr):\r
+ mrc p15, 0, r0, c1, c0, 1\r
+ bx lr \r
+\r
+ASM_PFX(ArmSetTTBR0):\r
+ mcr p15,0,r0,c2,c0,0\r
+ isb\r
+ bx lr\r
+\r
+ASM_PFX(ArmGetTTBR0BaseAddress):\r
+ mrc p15,0,r0,c2,c0,0\r
+ LoadConstantToReg(0xFFFFC000, r1)\r
+ and r0, r0, r1\r
+ isb\r
+ bx lr\r
+\r
+//\r
+//VOID\r
+//ArmUpdateTranslationTableEntry (\r
+// IN VOID *TranslationTableEntry // R0\r
+// IN VOID *MVA // R1\r
+// );\r
+ASM_PFX(ArmUpdateTranslationTableEntry):\r
+ mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA\r
+ dsb\r
+ mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA \r
+ mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp\r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+ASM_PFX(ArmInvalidateTlb):\r
+ mov r0,#0\r
+ mcr p15,0,r0,c8,c7,0\r
+ mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp\r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+ASM_PFX(ArmReadNsacr):\r
+ mrc p15, 0, r0, c1, c1, 2\r
+ bx lr\r
+\r
+ASM_PFX(ArmWriteNsacr):\r
+ mcr p15, 0, r0, c1, c1, 2\r
+ bx lr\r
+\r
+ASM_PFX(ArmReadScr):\r
+ mrc p15, 0, r0, c1, c1, 0\r
+ bx lr\r
+\r
+ASM_PFX(ArmWriteScr):\r
+ mcr p15, 0, r0, c1, c1, 0\r
+ bx lr\r
+\r
+ASM_PFX(ArmReadMVBar):\r
+ mrc p15, 0, r0, c12, c0, 1\r
+ bx lr\r
+\r
+ASM_PFX(ArmWriteMVBar):\r
+ mcr p15, 0, r0, c12, c0, 1\r
+ bx lr\r
+\r
+ASM_PFX(ArmCallWFE):\r
+ wfe\r
+ bx lr\r
+\r
+ASM_PFX(ArmCallSEV):\r
+ sev\r
+ bx lr\r
+\r
+ASM_PFX(ArmReadSctlr):\r
+ mrc p15, 0, R0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r
+ bx lr\r
+\r
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
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