Sync up ArmPkg with patch from mailing list. Changed name of BdsLib.h to BdsUnixLib...

[mirror_edk2.git] / ArmPkg / Library / ArmLib / Common / ArmLibSupport.asm

diff --git a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
index 459ebd44c887955c5cb3c5c59de765e8cf1e217a..cf7605f45aeee05c55b8bdd56f032fe94e28cf31 100644 (file)
--- a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
+++ b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
@@ -15,6 +15,7 @@
 
     EXPORT  Cp15IdCode
     EXPORT  Cp15CacheInfo
+    EXPORT  ArmIsMPCore
     EXPORT  ArmEnableInterrupts
     EXPORT  ArmDisableInterrupts
     EXPORT  ArmGetInterruptState
@@ -22,8 +23,8 @@
     EXPORT  ArmDisableFiq
     EXPORT  ArmGetFiqState
     EXPORT  ArmInvalidateTlb
-    EXPORT  ArmSetTranslationTableBaseAddress
-    EXPORT  ArmGetTranslationTableBaseAddress
+    EXPORT  ArmSetTTBR0
+    EXPORT  ArmGetTTBR0BaseAddress
     EXPORT  ArmSetDomainAccessControl
     EXPORT  CPSRMaskInsert
     EXPORT  CPSRRead
@@ -38,6 +39,14 @@ Cp15CacheInfo
   mrc     p15,0,R0,c0,c0,1
   bx      LR
 
+ArmIsMPCore
+  mrc     p15,0,R0,c0,c0,5
+  # Get Multiprocessing extension (bit31) & U bit (bit30)
+  and     R0, R0, #0xC0000000
+  # if bit30 == 0 then the processor is part of a multiprocessor system)
+  and     R0, R0, #0x80000000
+  bx      LR
+
 ArmEnableInterrupts
        mrs     R0,CPSR
        bic     R0,R0,#0x80             ;Enable IRQ interrupts
@@ -87,12 +96,13 @@ ArmInvalidateTlb
   mcr     p15,0,r0,c8,c7,0
   bx      lr
 
-ArmSetTranslationTableBaseAddress
+ArmSetTTBR0
   mcr     p15,0,r0,c2,c0,0
   bx      lr
 
-ArmGetTranslationTableBaseAddress
+ArmGetTTBR0BaseAddress
   mrc     p15,0,r0,c2,c0,0
+  and     r0, r0, #0xFFFFC000
   bx      lr
 
 ArmSetDomainAccessControl