-//------------------------------------------------------------------------------
-//
-// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
-//
-// All rights reserved. This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//------------------------------------------------------------------------------
-
-
- EXPORT Cp15IdCode
- EXPORT Cp15CacheInfo
- EXPORT ArmEnableInterrupts
- EXPORT ArmDisableInterrupts
- EXPORT ArmGetInterruptState
- EXPORT ArmInvalidateTlb
- EXPORT ArmSetTranslationTableBaseAddress
- EXPORT ArmSetDomainAccessControl
- EXPORT CPSRMaskInsert
- EXPORT CPSRRead
-
- AREA ArmLibSupport, CODE, READONLY
-
-Cp15IdCode
- mrc p15,0,R0,c0,c0,0
- bx LR
-
-Cp15CacheInfo
- mrc p15,0,R0,c0,c0,1
- bx LR
-
-ArmEnableInterrupts
- mrs R0,CPSR
- bic R0,R0,#0x80 ;Enable IRQ interrupts
- msr CPSR_c,R0
- bx LR
-
-ArmDisableInterrupts
- mrs R0,CPSR
- orr R1,R0,#0x80 ;Disable IRQ interrupts
- msr CPSR_c,R1
- tst R0,#0x80
- moveq R0,#1
- movne R0,#0
- bx LR
-
-ArmGetInterruptState
- mrs R0,CPSR
- tst R0,#0x80 ;Check if IRQ is enabled.
- moveq R0,#1
- movne R0,#0
- bx LR
-
-ArmInvalidateTlb
- mov r0,#0
- mcr p15,0,r0,c8,c7,0
- bx lr
-
-ArmSetTranslationTableBaseAddress
- mcr p15,0,r0,c2,c0,0
- bx lr
-
-ArmSetDomainAccessControl
- mcr p15,0,r0,c3,c0,0
- bx lr
-
-CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert
- stmfd sp!, {r4-r12, lr} ; save all the banked registers
- mov r3, sp ; copy the stack pointer into a non-banked register
- mrs r2, cpsr ; read the cpsr
- bic r2, r2, r0 ; clear mask in the cpsr
- and r1, r1, r0 ; clear bits outside the mask in the input
- orr r2, r2, r1 ; set field
- msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch)
- mov sp, r3 ; restore stack pointer
- ldmfd sp!, {r4-r12, lr} ; restore registers
- bx lr ; return (hopefully thumb-safe!)
-
-CPSRRead
- mrs r0, cpsr
- bx lr
-
- END
-
-
+//------------------------------------------------------------------------------ \r
+//\r
+// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+#include <AsmMacroIoLib.h>\r
+ \r
+ INCLUDE AsmMacroIoLib.inc\r
+\r
+#ifdef ARM_CPU_ARMv6\r
+// No memory barriers for ARMv6\r
+#define isb\r
+#define dsb\r
+#endif\r
+\r
+ EXPORT Cp15IdCode\r
+ EXPORT Cp15CacheInfo\r
+ EXPORT ArmGetInterruptState\r
+ EXPORT ArmGetFiqState\r
+ EXPORT ArmGetTTBR0BaseAddress\r
+ EXPORT ArmSetTTBR0\r
+ EXPORT ArmSetDomainAccessControl\r
+ EXPORT CPSRMaskInsert\r
+ EXPORT CPSRRead\r
+ EXPORT ArmWriteCPACR\r
+ EXPORT ArmWriteAuxCr\r
+ EXPORT ArmReadAuxCr\r
+ EXPORT ArmInvalidateTlb\r
+ EXPORT ArmUpdateTranslationTableEntry\r
+ EXPORT ArmWriteNsacr\r
+ EXPORT ArmWriteScr\r
+ EXPORT ArmWriteVMBar\r
+\r
+ AREA ArmLibSupport, CODE, READONLY\r
+\r
+Cp15IdCode\r
+ mrc p15,0,R0,c0,c0,0\r
+ bx LR\r
+\r
+Cp15CacheInfo\r
+ mrc p15,0,R0,c0,c0,1\r
+ bx LR\r
+\r
+ArmGetInterruptState\r
+ mrs R0,CPSR\r
+ tst R0,#0x80 // Check if IRQ is enabled.\r
+ moveq R0,#1\r
+ movne R0,#0\r
+ bx LR\r
+\r
+ArmGetFiqState\r
+ mrs R0,CPSR\r
+ tst R0,#0x40 // Check if FIQ is enabled.\r
+ moveq R0,#1\r
+ movne R0,#0\r
+ bx LR\r
+\r
+ArmSetDomainAccessControl\r
+ mcr p15,0,r0,c3,c0,0\r
+ bx lr\r
+\r
+CPSRMaskInsert // on entry, r0 is the mask and r1 is the field to insert\r
+ stmfd sp!, {r4-r12, lr} // save all the banked registers\r
+ mov r3, sp // copy the stack pointer into a non-banked register\r
+ mrs r2, cpsr // read the cpsr\r
+ bic r2, r2, r0 // clear mask in the cpsr\r
+ and r1, r1, r0 // clear bits outside the mask in the input\r
+ orr r2, r2, r1 // set field\r
+ msr cpsr_cxsf, r2 // write back cpsr (may have caused a mode switch)\r
+ isb\r
+ mov sp, r3 // restore stack pointer\r
+ ldmfd sp!, {r4-r12, lr} // restore registers\r
+ bx lr // return (hopefully thumb-safe!) // return (hopefully thumb-safe!)\r
+\r
+CPSRRead\r
+ mrs r0, cpsr\r
+ bx lr\r
+\r
+ArmWriteCPACR\r
+ mcr p15, 0, r0, c1, c0, 2\r
+ bx lr\r
+\r
+ArmWriteAuxCr\r
+ mcr p15, 0, r0, c1, c0, 1\r
+ bx lr\r
+\r
+ArmReadAuxCr\r
+ mrc p15, 0, r0, c1, c0, 1\r
+ bx lr \r
+\r
+ArmSetTTBR0\r
+ mcr p15,0,r0,c2,c0,0\r
+ isb\r
+ bx lr\r
+\r
+ArmGetTTBR0BaseAddress\r
+ mrc p15,0,r0,c2,c0,0\r
+ LoadConstantToReg(0xFFFFC000, r1)\r
+ and r0, r0, r1\r
+ isb\r
+ bx lr\r
+\r
+//\r
+//VOID\r
+//ArmUpdateTranslationTableEntry (\r
+// IN VOID *TranslationTableEntry // R0\r
+// IN VOID *MVA // R1\r
+// );\r
+ArmUpdateTranslationTableEntry\r
+ mcr p15,0,R0,c7,c14,1 // DCCIMVAC Clean data cache by MVA\r
+ dsb\r
+ mcr p15,0,R1,c8,c7,1 // TLBIMVA TLB Invalidate MVA\r
+ mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp\r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+ArmInvalidateTlb\r
+ mov r0,#0\r
+ mcr p15,0,r0,c8,c7,0\r
+ mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp\r
+ dsb\r
+ isb\r
+ bx lr\r
+\r
+ArmWriteNsacr\r
+ mcr p15, 0, r0, c1, c1, 2\r
+ bx lr\r
+\r
+ArmWriteScr\r
+ mcr p15, 0, r0, c1, c1, 0\r
+ bx lr\r
+\r
+ArmWriteVMBar\r
+ mcr p15, 0, r0, c12, c0, 1\r
+ bx lr\r
+ \r
+ END\r
projects / mirror_edk2.git / blobdiff