ArmPkg/CpuDxe: move PageAttributeToGcdAttribute() out of ArmMmuLib

[mirror_edk2.git] / ArmPkg / Library / ArmMmuLib / AArch64 / ArmMmuLibCore.c

diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
index 3b10ef58f0a28aa04ca4fbd92cd74e2c0e0a4cca..d16e847218b7495c871675e289a561485ac02241 100644 (file)
--- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
+++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
@@ -57,51 +57,6 @@ ArmMemoryAttributeToPageAttribute (
   }\r
 }\r
 \r
-UINT64\r
-PageAttributeToGcdAttribute (\r
-  IN UINT64 PageAttributes\r
-  )\r
-{\r
-  UINT64  GcdAttributes;\r
-\r
-  switch (PageAttributes & TT_ATTR_INDX_MASK) {\r
-  case TT_ATTR_INDX_DEVICE_MEMORY:\r
-    GcdAttributes = EFI_MEMORY_UC;\r
-    break;\r
-  case TT_ATTR_INDX_MEMORY_NON_CACHEABLE:\r
-    GcdAttributes = EFI_MEMORY_WC;\r
-    break;\r
-  case TT_ATTR_INDX_MEMORY_WRITE_THROUGH:\r
-    GcdAttributes = EFI_MEMORY_WT;\r
-    break;\r
-  case TT_ATTR_INDX_MEMORY_WRITE_BACK:\r
-    GcdAttributes = EFI_MEMORY_WB;\r
-    break;\r
-  default:\r
-    DEBUG ((DEBUG_ERROR,\r
-      "PageAttributeToGcdAttribute: PageAttributes:0x%lX not supported.\n",\r
-      PageAttributes));\r
-    ASSERT (0);\r
-    // The Global Coherency Domain (GCD) value is defined as a bit set.\r
-    // Returning 0 means no attribute has been set.\r
-    GcdAttributes = 0;\r
-  }\r
-\r
-  // Determine protection attributes\r
-  if (((PageAttributes & TT_AP_MASK) == TT_AP_NO_RO) ||\r
-      ((PageAttributes & TT_AP_MASK) == TT_AP_RO_RO)) {\r
-    // Read only cases map to write-protect\r
-    GcdAttributes |= EFI_MEMORY_RO;\r
-  }\r
-\r
-  // Process eXecute Never attribute\r
-  if ((PageAttributes & (TT_PXN_MASK | TT_UXN_MASK)) != 0) {\r
-    GcdAttributes |= EFI_MEMORY_XP;\r
-  }\r
-\r
-  return GcdAttributes;\r
-}\r
-\r
 #define MIN_T0SZ        16\r
 #define BITS_PER_LEVEL  9\r
 \r