ArmPkg/ArmMmuLib AARCH64: get rid of needless TLB invalidation

[mirror_edk2.git] / ArmPkg / Library / ArmMmuLib / AArch64 / ArmMmuLibCore.c

diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
index d66df3e17a02a17c71b4ff947963de3f584320a6..3498f520e39ab7f0a4d26873bd312d52357aad47 100644 (file)
--- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
+++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
@@ -129,13 +129,14 @@ STATIC
 VOID\r
 ReplaceLiveEntry (\r
   IN  UINT64  *Entry,\r
-  IN  UINT64  Value\r
+  IN  UINT64  Value,\r
+  IN  UINT64  RegionStart\r
   )\r
 {\r
   if (!ArmMmuEnabled ()) {\r
     *Entry = Value;\r
   } else {\r
-    ArmReplaceLiveTranslationEntry (Entry, Value);\r
+    ArmReplaceLiveTranslationEntry (Entry, Value, RegionStart);\r
   }\r
 }\r
 \r
@@ -296,7 +297,8 @@ GetBlockEntryListFromAddress (
 \r
         // Fill the BlockEntry with the new TranslationTable\r
         ReplaceLiveEntry (BlockEntry,\r
-          ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TableAttributes | TT_TYPE_TABLE_ENTRY);\r
+          (UINTN)TranslationTable | TableAttributes | TT_TYPE_TABLE_ENTRY,\r
+          RegionStart);\r
       }\r
     } else {\r
       if (IndexLevel != PageLevel) {\r
@@ -375,6 +377,8 @@ UpdateRegionMapping (
       *BlockEntry &= BlockEntryMask;\r
       *BlockEntry |= (RegionStart & TT_ADDRESS_MASK_BLOCK_ENTRY) | Attributes | Type;\r
 \r
+      ArmUpdateTranslationTableEntry (BlockEntry, (VOID *)RegionStart);\r
+\r
       // Go to the next BlockEntry\r
       RegionStart += BlockEntrySize;\r
       RegionLength -= BlockEntrySize;\r
@@ -487,9 +491,6 @@ ArmSetMemoryAttributes (
     return Status;\r
   }\r
 \r
-  // Invalidate all TLB entries so changes are synced\r
-  ArmInvalidateTlb ();\r
-\r
   return EFI_SUCCESS;\r
 }\r
 \r
@@ -512,9 +513,6 @@ SetMemoryRegionAttribute (
     return Status;\r
   }\r
 \r
-  // Invalidate all TLB entries so changes are synced\r
-  ArmInvalidateTlb ();\r
-\r
   return EFI_SUCCESS;\r
 }\r
 \r