#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
\r
-#define ID_MMFR0_SHARELVL_SHIFT 12\r
-#define ID_MMFR0_SHARELVL_MASK 0xf\r
-#define ID_MMFR0_SHARELVL_ONE 0\r
-#define ID_MMFR0_SHARELVL_TWO 1\r
+#define ID_MMFR0_SHARELVL_SHIFT 12\r
+#define ID_MMFR0_SHARELVL_MASK 0xf\r
+#define ID_MMFR0_SHARELVL_ONE 0\r
+#define ID_MMFR0_SHARELVL_TWO 1\r
\r
-#define ID_MMFR0_INNERSHR_SHIFT 28\r
-#define ID_MMFR0_INNERSHR_MASK 0xf\r
-#define ID_MMFR0_OUTERSHR_SHIFT 8\r
-#define ID_MMFR0_OUTERSHR_MASK 0xf\r
+#define ID_MMFR0_INNERSHR_SHIFT 28\r
+#define ID_MMFR0_INNERSHR_MASK 0xf\r
+#define ID_MMFR0_OUTERSHR_SHIFT 8\r
+#define ID_MMFR0_OUTERSHR_MASK 0xf\r
\r
-#define ID_MMFR0_SHR_IMP_UNCACHED 0\r
-#define ID_MMFR0_SHR_IMP_HW_COHERENT 1\r
-#define ID_MMFR0_SHR_IGNORED 0xf\r
+#define ID_MMFR0_SHR_IMP_UNCACHED 0\r
+#define ID_MMFR0_SHR_IMP_HW_COHERENT 1\r
+#define ID_MMFR0_SHR_IGNORED 0xf\r
\r
UINTN\r
EFIAPI\r
VOID\r
)\r
{\r
- UINTN Mmfr;\r
- UINTN Val;\r
+ UINTN Mmfr;\r
+ UINTN Val;\r
\r
if (FeaturePcdGet (PcdNormalMemoryNonshareableOverride)) {\r
return TRUE;\r
//\r
Mmfr = ArmReadIdMmfr0 ();\r
switch ((Mmfr >> ID_MMFR0_SHARELVL_SHIFT) & ID_MMFR0_SHARELVL_MASK) {\r
- case ID_MMFR0_SHARELVL_ONE:\r
- // one level of shareability\r
- Val = (Mmfr >> ID_MMFR0_OUTERSHR_SHIFT) & ID_MMFR0_OUTERSHR_MASK;\r
- break;\r
- case ID_MMFR0_SHARELVL_TWO:\r
- // two levels of shareability\r
- Val = (Mmfr >> ID_MMFR0_INNERSHR_SHIFT) & ID_MMFR0_INNERSHR_MASK;\r
- break;\r
- default:\r
- // unexpected value -> shareable is the safe option\r
- ASSERT (FALSE);\r
- return FALSE;\r
+ case ID_MMFR0_SHARELVL_ONE:\r
+ // one level of shareability\r
+ Val = (Mmfr >> ID_MMFR0_OUTERSHR_SHIFT) & ID_MMFR0_OUTERSHR_MASK;\r
+ break;\r
+ case ID_MMFR0_SHARELVL_TWO:\r
+ // two levels of shareability\r
+ Val = (Mmfr >> ID_MMFR0_INNERSHR_SHIFT) & ID_MMFR0_INNERSHR_MASK;\r
+ break;\r
+ default:\r
+ // unexpected value -> shareable is the safe option\r
+ ASSERT (FALSE);\r
+ return FALSE;\r
}\r
+\r
return Val != ID_MMFR0_SHR_IMP_HW_COHERENT;\r
}\r
\r
STATIC\r
VOID\r
PopulateLevel2PageTable (\r
- IN UINT32 *SectionEntry,\r
- IN UINT32 PhysicalBase,\r
- IN UINT32 RemainLength,\r
- IN ARM_MEMORY_REGION_ATTRIBUTES Attributes\r
+ IN UINT32 *SectionEntry,\r
+ IN UINT32 PhysicalBase,\r
+ IN UINT32 RemainLength,\r
+ IN ARM_MEMORY_REGION_ATTRIBUTES Attributes\r
)\r
{\r
- UINT32* PageEntry;\r
+ UINT32 *PageEntry;\r
UINT32 Pages;\r
UINT32 Index;\r
UINT32 PageAttributes;\r
break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:\r
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:\r
- PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;\r
+ PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;\r
PageAttributes &= ~TT_DESCRIPTOR_PAGE_S_SHARED;\r
break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:\r
// Level 2 Translation Table to it\r
if (*SectionEntry != 0) {\r
// The entry must be a page table. Otherwise it exists an overlapping in the memory map\r
- if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(*SectionEntry)) {\r
+ if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE (*SectionEntry)) {\r
TranslationTable = *SectionEntry & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK;\r
} else if ((*SectionEntry & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) {\r
// Case where a virtual memory map descriptor overlapped a section entry\r
// Allocate a Level2 Page Table for this Section\r
TranslationTable = (UINTN)AllocateAlignedPages (\r
EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_PAGE_SIZE),\r
- TRANSLATION_TABLE_PAGE_ALIGNMENT);\r
+ TRANSLATION_TABLE_PAGE_ALIGNMENT\r
+ );\r
\r
// Translate the Section Descriptor into Page Descriptor\r
SectionDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttributesToPageAttributes (*SectionEntry, FALSE);\r
\r
- BaseSectionAddress = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(*SectionEntry);\r
+ BaseSectionAddress = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (*SectionEntry);\r
\r
//\r
// Make sure we are not inadvertently hitting in the caches\r
// when populating the page tables\r
//\r
- InvalidateDataCacheRange ((VOID *)TranslationTable,\r
- TRANSLATION_TABLE_PAGE_SIZE);\r
+ InvalidateDataCacheRange (\r
+ (VOID *)TranslationTable,\r
+ TRANSLATION_TABLE_PAGE_SIZE\r
+ );\r
\r
// Populate the new Level2 Page Table for the section\r
- PageEntry = (UINT32*)TranslationTable;\r
+ PageEntry = (UINT32 *)TranslationTable;\r
for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {\r
- PageEntry[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseSectionAddress + (Index << 12)) | SectionDescriptor;\r
+ PageEntry[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS (BaseSectionAddress + (Index << 12)) | SectionDescriptor;\r
}\r
\r
// Overwrite the section entry to point to the new Level2 Translation Table\r
*SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) |\r
- (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes) ? (1 << 3) : 0) |\r
- TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r
+ (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE (Attributes) ? (1 << 3) : 0) |\r
+ TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r
} else {\r
// We do not support the other section type (16MB Section)\r
- ASSERT(0);\r
+ ASSERT (0);\r
return;\r
}\r
} else {\r
TranslationTable = (UINTN)AllocateAlignedPages (\r
EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_PAGE_SIZE),\r
- TRANSLATION_TABLE_PAGE_ALIGNMENT);\r
+ TRANSLATION_TABLE_PAGE_ALIGNMENT\r
+ );\r
//\r
// Make sure we are not inadvertently hitting in the caches\r
// when populating the page tables\r
//\r
- InvalidateDataCacheRange ((VOID *)TranslationTable,\r
- TRANSLATION_TABLE_PAGE_SIZE);\r
+ InvalidateDataCacheRange (\r
+ (VOID *)TranslationTable,\r
+ TRANSLATION_TABLE_PAGE_SIZE\r
+ );\r
ZeroMem ((VOID *)TranslationTable, TRANSLATION_TABLE_PAGE_SIZE);\r
\r
*SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) |\r
- (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes) ? (1 << 3) : 0) |\r
- TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r
+ (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE (Attributes) ? (1 << 3) : 0) |\r
+ TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r
}\r
\r
FirstPageOffset = (PhysicalBase & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;\r
- PageEntry = (UINT32 *)TranslationTable + FirstPageOffset;\r
- Pages = RemainLength / TT_DESCRIPTOR_PAGE_SIZE;\r
+ PageEntry = (UINT32 *)TranslationTable + FirstPageOffset;\r
+ Pages = RemainLength / TT_DESCRIPTOR_PAGE_SIZE;\r
\r
ASSERT (FirstPageOffset + Pages <= TRANSLATION_TABLE_PAGE_COUNT);\r
\r
for (Index = 0; Index < Pages; Index++) {\r
- *PageEntry++ = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(PhysicalBase) | PageAttributes;\r
+ *PageEntry++ = TT_DESCRIPTOR_PAGE_BASE_ADDRESS (PhysicalBase) | PageAttributes;\r
PhysicalBase += TT_DESCRIPTOR_PAGE_SIZE;\r
}\r
\r
// [speculatively] since the previous invalidate are evicted again.\r
//\r
ArmDataMemoryBarrier ();\r
- InvalidateDataCacheRange ((UINT32 *)TranslationTable + FirstPageOffset,\r
- RemainLength / TT_DESCRIPTOR_PAGE_SIZE * sizeof (*PageEntry));\r
+ InvalidateDataCacheRange (\r
+ (UINT32 *)TranslationTable + FirstPageOffset,\r
+ RemainLength / TT_DESCRIPTOR_PAGE_SIZE * sizeof (*PageEntry)\r
+ );\r
}\r
\r
STATIC\r
UINT64 RemainLength;\r
UINT32 PageMapLength;\r
\r
- ASSERT(MemoryRegion->Length > 0);\r
+ ASSERT (MemoryRegion->Length > 0);\r
\r
if (MemoryRegion->PhysicalBase >= SIZE_4GB) {\r
return;\r
}\r
\r
PhysicalBase = (UINT32)MemoryRegion->PhysicalBase;\r
- RemainLength = MIN(MemoryRegion->Length, SIZE_4GB - PhysicalBase);\r
+ RemainLength = MIN (MemoryRegion->Length, SIZE_4GB - PhysicalBase);\r
\r
switch (MemoryRegion->Attributes) {\r
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:\r
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);\r
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK (0);\r
break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:\r
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);\r
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK (0);\r
Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED;\r
break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:\r
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);\r
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH (0);\r
break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:\r
- Attributes = TT_DESCRIPTOR_SECTION_DEVICE(0);\r
+ Attributes = TT_DESCRIPTOR_SECTION_DEVICE (0);\r
break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:\r
- Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);\r
+ Attributes = TT_DESCRIPTOR_SECTION_UNCACHED (0);\r
break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:\r
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);\r
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK (1);\r
break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:\r
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);\r
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK (1);\r
Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED;\r
break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:\r
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);\r
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH (1);\r
break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:\r
- Attributes = TT_DESCRIPTOR_SECTION_DEVICE(1);\r
+ Attributes = TT_DESCRIPTOR_SECTION_DEVICE (1);\r
break;\r
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:\r
- Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);\r
+ Attributes = TT_DESCRIPTOR_SECTION_UNCACHED (1);\r
break;\r
default:\r
- Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);\r
+ Attributes = TT_DESCRIPTOR_SECTION_UNCACHED (0);\r
break;\r
}\r
\r
}\r
\r
// Get the first section entry for this mapping\r
- SectionEntry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);\r
+ SectionEntry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS (TranslationTable, MemoryRegion->VirtualBase);\r
\r
while (RemainLength != 0) {\r
- if (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE == 0 &&\r
- RemainLength >= TT_DESCRIPTOR_SECTION_SIZE) {\r
+ if ((PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE == 0) &&\r
+ (RemainLength >= TT_DESCRIPTOR_SECTION_SIZE))\r
+ {\r
// Case: Physical address aligned on the Section Size (1MB) && the length\r
// is greater than the Section Size\r
- *SectionEntry = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;\r
+ *SectionEntry = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (PhysicalBase) | Attributes;\r
\r
//\r
// Issue a DMB to ensure that the page table entry update made it to\r
PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;\r
RemainLength -= TT_DESCRIPTOR_SECTION_SIZE;\r
} else {\r
- PageMapLength = MIN ((UINT32)RemainLength, TT_DESCRIPTOR_SECTION_SIZE -\r
- (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE));\r
+ PageMapLength = MIN (\r
+ (UINT32)RemainLength,\r
+ TT_DESCRIPTOR_SECTION_SIZE -\r
+ (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE)\r
+ );\r
\r
// Case: Physical address aligned on the Section Size (1MB) && the length\r
// does not fill a section\r
// Case: Physical address NOT aligned on the Section Size (1MB)\r
- PopulateLevel2PageTable (SectionEntry, PhysicalBase, PageMapLength,\r
- MemoryRegion->Attributes);\r
+ PopulateLevel2PageTable (\r
+ SectionEntry,\r
+ PhysicalBase,\r
+ PageMapLength,\r
+ MemoryRegion->Attributes\r
+ );\r
\r
//\r
// Issue a DMB to ensure that the page table entry update made it to\r
EFIAPI\r
ArmConfigureMmu (\r
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,\r
- OUT VOID **TranslationTableBase OPTIONAL,\r
+ OUT VOID **TranslationTableBase OPTIONAL,\r
OUT UINTN *TranslationTableSize OPTIONAL\r
)\r
{\r
- VOID *TranslationTable;\r
- UINT32 TTBRAttributes;\r
+ VOID *TranslationTable;\r
+ UINT32 TTBRAttributes;\r
\r
TranslationTable = AllocateAlignedPages (\r
EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_SECTION_SIZE),\r
- TRANSLATION_TABLE_SECTION_ALIGNMENT);\r
+ TRANSLATION_TABLE_SECTION_ALIGNMENT\r
+ );\r
if (TranslationTable == NULL) {\r
return RETURN_OUT_OF_RESOURCES;\r
}\r
//\r
ArmSetTTBCR (0);\r
\r
- ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) |\r
- DOMAIN_ACCESS_CONTROL_NONE(14) |\r
- DOMAIN_ACCESS_CONTROL_NONE(13) |\r
- DOMAIN_ACCESS_CONTROL_NONE(12) |\r
- DOMAIN_ACCESS_CONTROL_NONE(11) |\r
- DOMAIN_ACCESS_CONTROL_NONE(10) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 9) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 8) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 7) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 6) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 5) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 4) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 3) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 2) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 1) |\r
- DOMAIN_ACCESS_CONTROL_CLIENT(0));\r
-\r
- ArmEnableInstructionCache();\r
- ArmEnableDataCache();\r
- ArmEnableMmu();\r
+ ArmSetDomainAccessControl (\r
+ DOMAIN_ACCESS_CONTROL_NONE (15) |\r
+ DOMAIN_ACCESS_CONTROL_NONE (14) |\r
+ DOMAIN_ACCESS_CONTROL_NONE (13) |\r
+ DOMAIN_ACCESS_CONTROL_NONE (12) |\r
+ DOMAIN_ACCESS_CONTROL_NONE (11) |\r
+ DOMAIN_ACCESS_CONTROL_NONE (10) |\r
+ DOMAIN_ACCESS_CONTROL_NONE (9) |\r
+ DOMAIN_ACCESS_CONTROL_NONE (8) |\r
+ DOMAIN_ACCESS_CONTROL_NONE (7) |\r
+ DOMAIN_ACCESS_CONTROL_NONE (6) |\r
+ DOMAIN_ACCESS_CONTROL_NONE (5) |\r
+ DOMAIN_ACCESS_CONTROL_NONE (4) |\r
+ DOMAIN_ACCESS_CONTROL_NONE (3) |\r
+ DOMAIN_ACCESS_CONTROL_NONE (2) |\r
+ DOMAIN_ACCESS_CONTROL_NONE (1) |\r
+ DOMAIN_ACCESS_CONTROL_CLIENT (0)\r
+ );\r
+\r
+ ArmEnableInstructionCache ();\r
+ ArmEnableDataCache ();\r
+ ArmEnableMmu ();\r
return RETURN_SUCCESS;\r
}\r
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