-//------------------------------------------------------------------------------
-//
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-//
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//------------------------------------------------------------------------------
-
-
- EXPORT __aeabi_uidiv
- EXPORT __aeabi_uidivmod
- EXPORT __aeabi_idiv
- EXPORT __aeabi_idivmod
-
- AREA Math, CODE, READONLY
-
-;
-;UINT32
-;EFIAPI
-;__aeabi_uidivmode (
-; IN UINT32 Dividen
-; IN UINT32 Divisor
-; );
-;
-
-__aeabi_uidiv
-__aeabi_uidivmod
- RSBS r12, r1, r0, LSR #4
- MOV r2, #0
- BCC __arm_div4
- RSBS r12, r1, r0, LSR #8
- BCC __arm_div8
- MOV r3, #0
- B __arm_div_large
-
-;
-;INT32
-;EFIAPI
-;__aeabi_idivmode (
-; IN INT32 Dividen
-; IN INT32 Divisor
-; );
-;
-__aeabi_idiv
-__aeabi_idivmod
- ORRS r12, r0, r1
- BMI __arm_div_negative
- RSBS r12, r1, r0, LSR #1
- MOV r2, #0
- BCC __arm_div1
- RSBS r12, r1, r0, LSR #4
- BCC __arm_div4
- RSBS r12, r1, r0, LSR #8
- BCC __arm_div8
- MOV r3, #0
- B __arm_div_large
-__arm_div8
- RSBS r12, r1, r0, LSR #7
- SUBCS r0, r0, r1, LSL #7
- ADC r2, r2, r2
- RSBS r12, r1, r0,LSR #6
- SUBCS r0, r0, r1, LSL #6
- ADC r2, r2, r2
- RSBS r12, r1, r0, LSR #5
- SUBCS r0, r0, r1, LSL #5
- ADC r2, r2, r2
- RSBS r12, r1, r0, LSR #4
- SUBCS r0, r0, r1, LSL #4
- ADC r2, r2, r2
-__arm_div4
- RSBS r12, r1, r0, LSR #3
- SUBCS r0, r0, r1, LSL #3
- ADC r2, r2, r2
- RSBS r12, r1, r0, LSR #2
- SUBCS r0, r0, r1, LSL #2
- ADCS r2, r2, r2
- RSBS r12, r1, r0, LSR #1
- SUBCS r0, r0, r1, LSL #1
- ADC r2, r2, r2
-__arm_div1
- SUBS r1, r0, r1
- MOVCC r1, r0
- ADC r0, r2, r2
- BX r14
-__arm_div_negative
- ANDS r2, r1, #0x80000000
- RSBMI r1, r1, #0
- EORS r3, r2, r0, ASR #32
- RSBCS r0, r0, #0
- RSBS r12, r1, r0, LSR #4
- BCC label1
- RSBS r12, r1, r0, LSR #8
- BCC label2
-__arm_div_large
- LSL r1, r1, #6
- RSBS r12, r1, r0, LSR #8
- ORR r2, r2, #0xfc000000
- BCC label2
- LSL r1, r1, #6
- RSBS r12, r1, r0, LSR #8
- ORR r2, r2, #0x3f00000
- BCC label2
- LSL r1, r1, #6
- RSBS r12, r1, r0, LSR #8
- ORR r2, r2, #0xfc000
- ORRCS r2, r2, #0x3f00
- LSLCS r1, r1, #6
- RSBS r12, r1, #0
- BCS __aeabi_idiv0
-label3
- LSRCS r1, r1, #6
-label2
- RSBS r12, r1, r0, LSR #7
- SUBCS r0, r0, r1, LSL #7
- ADC r2, r2, r2
- RSBS r12, r1, r0, LSR #6
- SUBCS r0, r0, r1, LSL #6
- ADC r2, r2, r2
- RSBS r12, r1, r0, LSR #5
- SUBCS r0, r0, r1, LSL #5
- ADC r2, r2, r2
- RSBS r12, r1, r0, LSR #4
- SUBCS r0, r0, r1, LSL #4
- ADC r2, r2, r2
-label1
- RSBS r12, r1, r0, LSR #3
- SUBCS r0, r0, r1, LSL #3
- ADC r2, r2, r2
- RSBS r12, r1, r0, LSR #2
- SUBCS r0, r0, r1, LSL #2
- ADCS r2, r2, r2
- BCS label3
- RSBS r12, r1, r0, LSR #1
- SUBCS r0, r0, r1, LSL #1
- ADC r2, r2, r2
- SUBS r1, r0, r1
- MOVCC r1, r0
- ADC r0, r2, r2
- ASRS r3, r3, #31
- RSBMI r0, r0, #0
- RSBCS r1, r1, #0
- BX r14
-
- ; What to do about division by zero? For now, just return.
-__aeabi_idiv0
- BX r14
-
- END
-
+//------------------------------------------------------------------------------\r
+//\r
+// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+// Copyright (c) 2018, Pete Batard. All rights reserved.<BR>\r
+//\r
+// SPDX-License-Identifier: BSD-2-Clause-Patent\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+\r
+ EXPORT __aeabi_uidiv\r
+ EXPORT __aeabi_uidivmod\r
+ EXPORT __aeabi_idiv\r
+ EXPORT __aeabi_idivmod\r
+ EXPORT __rt_udiv\r
+ EXPORT __rt_sdiv\r
+\r
+ AREA Math, CODE, READONLY\r
+\r
+;\r
+;UINT32\r
+;EFIAPI\r
+;__aeabi_uidivmod (\r
+; IN UINT32 Dividend\r
+; IN UINT32 Divisor\r
+; );\r
+;\r
+__aeabi_uidiv\r
+__aeabi_uidivmod\r
+ RSBS r12, r1, r0, LSR #4\r
+ MOV r2, #0\r
+ BCC __arm_div4\r
+ RSBS r12, r1, r0, LSR #8\r
+ BCC __arm_div8\r
+ MOV r3, #0\r
+ B __arm_div_large\r
+\r
+;\r
+;UINT64\r
+;EFIAPI\r
+;__rt_udiv (\r
+; IN UINT32 Divisor,\r
+; IN UINT32 Dividend\r
+; );\r
+;\r
+__rt_udiv\r
+ ; Swap R0 and R1\r
+ MOV r12, r0\r
+ MOV r0, r1\r
+ MOV r1, r12\r
+ B __aeabi_uidivmod\r
+\r
+;\r
+;UINT64\r
+;EFIAPI\r
+;__rt_sdiv (\r
+; IN INT32 Divisor,\r
+; IN INT32 Dividend\r
+; );\r
+;\r
+__rt_sdiv\r
+ ; Swap R0 and R1\r
+ MOV r12, r0\r
+ MOV r0, r1\r
+ MOV r1, r12\r
+ B __aeabi_idivmod\r
+\r
+;\r
+;INT32\r
+;EFIAPI\r
+;__aeabi_idivmod (\r
+; IN INT32 Dividend\r
+; IN INT32 Divisor\r
+; );\r
+;\r
+__aeabi_idiv\r
+__aeabi_idivmod\r
+ ORRS r12, r0, r1\r
+ BMI __arm_div_negative\r
+ RSBS r12, r1, r0, LSR #1\r
+ MOV r2, #0\r
+ BCC __arm_div1\r
+ RSBS r12, r1, r0, LSR #4\r
+ BCC __arm_div4\r
+ RSBS r12, r1, r0, LSR #8\r
+ BCC __arm_div8\r
+ MOV r3, #0\r
+ B __arm_div_large\r
+__arm_div8\r
+ RSBS r12, r1, r0, LSR #7\r
+ SUBCS r0, r0, r1, LSL #7\r
+ ADC r2, r2, r2\r
+ RSBS r12, r1, r0,LSR #6\r
+ SUBCS r0, r0, r1, LSL #6\r
+ ADC r2, r2, r2\r
+ RSBS r12, r1, r0, LSR #5\r
+ SUBCS r0, r0, r1, LSL #5\r
+ ADC r2, r2, r2\r
+ RSBS r12, r1, r0, LSR #4\r
+ SUBCS r0, r0, r1, LSL #4\r
+ ADC r2, r2, r2\r
+__arm_div4\r
+ RSBS r12, r1, r0, LSR #3\r
+ SUBCS r0, r0, r1, LSL #3\r
+ ADC r2, r2, r2\r
+ RSBS r12, r1, r0, LSR #2\r
+ SUBCS r0, r0, r1, LSL #2\r
+ ADCS r2, r2, r2\r
+ RSBS r12, r1, r0, LSR #1\r
+ SUBCS r0, r0, r1, LSL #1\r
+ ADC r2, r2, r2\r
+__arm_div1\r
+ SUBS r1, r0, r1\r
+ MOVCC r1, r0\r
+ ADC r0, r2, r2\r
+ BX r14\r
+__arm_div_negative\r
+ ANDS r2, r1, #0x80000000\r
+ RSBMI r1, r1, #0\r
+ EORS r3, r2, r0, ASR #32\r
+ RSBCS r0, r0, #0\r
+ RSBS r12, r1, r0, LSR #4\r
+ BCC label1\r
+ RSBS r12, r1, r0, LSR #8\r
+ BCC label2\r
+__arm_div_large\r
+ LSL r1, r1, #6\r
+ RSBS r12, r1, r0, LSR #8\r
+ ORR r2, r2, #0xfc000000\r
+ BCC label2\r
+ LSL r1, r1, #6\r
+ RSBS r12, r1, r0, LSR #8\r
+ ORR r2, r2, #0x3f00000\r
+ BCC label2\r
+ LSL r1, r1, #6\r
+ RSBS r12, r1, r0, LSR #8\r
+ ORR r2, r2, #0xfc000\r
+ ORRCS r2, r2, #0x3f00\r
+ LSLCS r1, r1, #6\r
+ RSBS r12, r1, #0\r
+ BCS __aeabi_idiv0\r
+label3\r
+ LSRCS r1, r1, #6\r
+label2\r
+ RSBS r12, r1, r0, LSR #7\r
+ SUBCS r0, r0, r1, LSL #7\r
+ ADC r2, r2, r2\r
+ RSBS r12, r1, r0, LSR #6\r
+ SUBCS r0, r0, r1, LSL #6\r
+ ADC r2, r2, r2\r
+ RSBS r12, r1, r0, LSR #5\r
+ SUBCS r0, r0, r1, LSL #5\r
+ ADC r2, r2, r2\r
+ RSBS r12, r1, r0, LSR #4\r
+ SUBCS r0, r0, r1, LSL #4\r
+ ADC r2, r2, r2\r
+label1\r
+ RSBS r12, r1, r0, LSR #3\r
+ SUBCS r0, r0, r1, LSL #3\r
+ ADC r2, r2, r2\r
+ RSBS r12, r1, r0, LSR #2\r
+ SUBCS r0, r0, r1, LSL #2\r
+ ADCS r2, r2, r2\r
+ BCS label3\r
+ RSBS r12, r1, r0, LSR #1\r
+ SUBCS r0, r0, r1, LSL #1\r
+ ADC r2, r2, r2\r
+ SUBS r1, r0, r1\r
+ MOVCC r1, r0\r
+ ADC r0, r2, r2\r
+ ASRS r3, r3, #31\r
+ RSBMI r0, r0, #0\r
+ RSBCS r1, r1, #0\r
+ BX r14\r
+\r
+ ; What to do about division by zero? For now, just return.\r
+__aeabi_idiv0\r
+ BX r14\r
+\r
+ END\r
projects / mirror_edk2.git / blobdiff