#
#------------------------------------------------------------------------------
-\s\s.text
-\s\s.align 2
-\s\sGCC_ASM_EXPORT(__divsi3)
-\s\s
+ .text
+ .align 2
+ GCC_ASM_EXPORT(__divsi3)
+
ASM_PFX(__divsi3):
-\s\seor\s\sr3, r0, r0, asr #31
-\s\seor\s\sr2, r1, r1, asr #31
-\s\sstmfd\s\ssp!, {r4, r5, r7, lr}
-\s\smov\s\sr5, r0, asr #31
-\s\sadd\s\sr7, sp, #8
-\s\smov\s\sr4, r1, asr #31
-\s\ssub\s\sr0, r3, r0, asr #31
-\s\ssub\s\sr1, r2, r1, asr #31
-\s\sbl\s\sASM_PFX(__udivsi3)
-\s\seor\s\sr1, r5, r4
-\s\seor\s\sr0, r0, r1
-\s\srsb\s\sr0, r1, r0
-\s\sldmfd\s\ssp!, {r4, r5, r7, pc}
+ eor r3, r0, r0, asr #31
+ eor r2, r1, r1, asr #31
+ stmfd sp!, {r4, r5, r7, lr}
+ mov r5, r0, asr #31
+ add r7, sp, #8
+ mov r4, r1, asr #31
+ sub r0, r3, r0, asr #31
+ sub r1, r2, r1, asr #31
+ bl ASM_PFX(__udivsi3)
+ eor r1, r5, r4
+ eor r0, r0, r1
+ rsb r0, r1, r0
+ ldmfd sp!, {r4, r5, r7, pc}