/** @file\r
* Main file supporting the SEC Phase for Versatile Express\r
*\r
-* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
EFI_FFS_FILE_HEADER *FfsHeader;\r
PE_COFF_LOADER_IMAGE_CONTEXT ImageContext;\r
\r
- // Now we've got UART, make the check:\r
- // - The Vector table must be 32-byte aligned\r
- //Need to fix basetools ASSERT(((UINTN)DebugAgentVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);\r
+ // Now we've got UART, check the Debug Agent Vector Table\r
+ // Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure\r
+ // 'Align=4K' is defined into your FDF for this module.\r
+ ASSERT (((UINTN)DebugAgentVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);\r
ArmWriteVBar ((UINTN)DebugAgentVectorTable);\r
\r
// We use InitFlag to know if DebugAgent has been intialized from\r