/** @file\r
* Multiple APIC Description Table (MADT)\r
*\r
-* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.\r
+* Copyright (c) 2012 - 2015, ARM Limited. All rights reserved.\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
\r
#include "ArmPlatform.h"\r
#include <Library/AcpiLib.h>\r
+#include <Library/ArmLib.h>\r
#include <Library/PcdLib.h>\r
#include <IndustryStandard/Acpi.h>\r
\r
-#pragma pack (1)\r
+//\r
+// Multiple APIC Description Table\r
+//\r
+#ifdef ARM_JUNO_ACPI_5_0\r
+ #pragma pack (1)\r
+\r
+ typedef struct {\r
+ EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;\r
+ EFI_ACPI_5_0_GIC_STRUCTURE GicInterfaces[FixedPcdGet32 (PcdCoreCount)];\r
+ EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;\r
+ } EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE;\r
+\r
+ #pragma pack ()\r
\r
-typedef struct {\r
- EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;\r
- EFI_ACPI_5_0_GIC_STRUCTURE GicInterfaces[FixedPcdGet32 (PcdCoreCount)];\r
- EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;\r
-} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;\r
+ EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {\r
+ {\r
+ ARM_ACPI_HEADER (\r
+ EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,\r
+ EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE,\r
+ EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION\r
+ ),\r
+ //\r
+ // MADT specific fields\r
+ //\r
+ 0, // LocalApicAddress\r
+ 0, // Flags\r
+ },\r
+ {\r
+ // Format: EFI_ACPI_5_0_GIC_STRUCTURE_INIT(GicId, AcpiCpuId, Flags, PmuIrq, GicBase)\r
+ // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GIC Structure of\r
+ // ACPI v5.0).\r
+ // On Juno we can change the primary CPU changing the SCC register. It is not currently supported in the\r
+ // Trusted Firmware. When supported, we will need to code to dynamically change the ordering.\r
+ // For now we leave CPU2 (A53-0) at the first position.\r
+ // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses\r
+ // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.\r
+ EFI_ACPI_5_0_GIC_STRUCTURE_INIT(2, 0, EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-0\r
+ EFI_ACPI_5_0_GIC_STRUCTURE_INIT(3, 1, EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-1\r
+ EFI_ACPI_5_0_GIC_STRUCTURE_INIT(4, 2, EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-2\r
+ EFI_ACPI_5_0_GIC_STRUCTURE_INIT(5, 3, EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-3\r
+ EFI_ACPI_5_0_GIC_STRUCTURE_INIT(0, 4, EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A57-0\r
+ EFI_ACPI_5_0_GIC_STRUCTURE_INIT(1, 5, EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet32 (PcdGicInterruptInterfaceBase)) // A57-1\r
+ },\r
+ EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0)\r
+ };\r
+#else\r
+ #pragma pack (1)\r
\r
-#pragma pack ()\r
+ typedef struct {\r
+ EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;\r
+ EFI_ACPI_5_1_GIC_STRUCTURE GicInterfaces[FixedPcdGet32 (PcdCoreCount)];\r
+ EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;\r
+ EFI_ACPI_6_0_GIC_MSI_FRAME_STRUCTURE MsiFrame;\r
+ } EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE;\r
+\r
+ #pragma pack ()\r
+\r
+ EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {\r
+ {\r
+ ARM_ACPI_HEADER (\r
+ EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,\r
+ EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE,\r
+ EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION\r
+ ),\r
+ //\r
+ // MADT specific fields\r
+ //\r
+ 0, // LocalApicAddress\r
+ 0, // Flags\r
+ },\r
+ {\r
+ // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase,\r
+ // GsivId, GicRBase, Mpidr)\r
+ // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of\r
+ // ACPI v5.1).\r
+ // On Juno we can change the primary CPU changing the SCC register. It is not currently supported in the\r
+ // Trusted Firmware. When supported, we will need to code to dynamically change the ordering.\r
+ // For now we leave CPU2 (A53-0) at the first position.\r
+ // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses\r
+ // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.\r
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-0\r
+ 2, 0, GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
+ 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-1\r
+ 3, 1, GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
+ 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-2\r
+ 4, 2, GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
+ 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-3\r
+ 5, 3, GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
+ 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-0\r
+ 0, 4, GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
+ 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-1\r
+ 1, 5, GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
+ 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
+ },\r
+ EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0),\r
+ // Format: EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(GicMsiFrameId, PhysicalBaseAddress, Flags, SPICount, SPIBase)\r
+ EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0, ARM_JUNO_GIV2M_MSI_BASE, 0, ARM_JUNO_GIV2M_MSI_SPI_COUNT, ARM_JUNO_GIV2M_MSI_SPI_BASE)\r
+ };\r
+#endif\r
\r
//\r
-// Multiple APIC Description Table\r
+// Reference the table being generated to prevent the optimizer from removing the\r
+// data structure from the executable\r
//\r
-EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {\r
- {\r
- ARM_ACPI_HEADER (\r
- EFI_ACPI_1_0_APIC_SIGNATURE,\r
- EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE,\r
- EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION\r
- ),\r
- //\r
- // MADT specific fields\r
- //\r
- 0, // LocalApicAddress\r
- 0, // Flags\r
- },\r
- {\r
- // Format: EFI_ACPI_5_0_GIC_STRUCTURE_INIT(GicId, AcpiCpuId, Flags, PmuIrq, GicBase)\r
- // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GIC Structure of\r
- // ACPI v5.0).\r
- // On Juno we can change the primary CPU changing the SCC register. It is not currently supported in the\r
- // Trusted Firmware. When supported, we will need to code to dynamically change the ordering.\r
- // For now we leave CPU2 (A53-0) at the first position.\r
- // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses\r
- // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.\r
- EFI_ACPI_5_0_GIC_STRUCTURE_INIT(2, 2, EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-0\r
- EFI_ACPI_5_0_GIC_STRUCTURE_INIT(3, 3, EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-1\r
- EFI_ACPI_5_0_GIC_STRUCTURE_INIT(4, 4, EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-2\r
- EFI_ACPI_5_0_GIC_STRUCTURE_INIT(5, 5, EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-3\r
- EFI_ACPI_5_0_GIC_STRUCTURE_INIT(0, 0, EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A57-0\r
- EFI_ACPI_5_0_GIC_STRUCTURE_INIT(1, 1, EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet32 (PcdGicInterruptInterfaceBase)) // A57-1\r
- },\r
- EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0)\r
-};\r
-\r
-VOID*\r
-ReferenceAcpiTable (\r
- VOID\r
- )\r
-{\r
- //\r
- // Reference the table being generated to prevent the optimizer from removing the\r
- // data structure from the executable\r
- //\r
- return (VOID*)&Madt;\r
-}\r
+VOID* CONST ReferenceAcpiTable = &Madt;\r
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