+++ /dev/null
-/** @file\r
-* Header containing the structure specific to the Xpress-RICH3 PCIe Root Complex\r
-*\r
-* Copyright (c) 2011-2015, ARM Ltd. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#ifndef __PCIHOSTBRIDGE_H\r
-#define __PCIHOSTBRIDGE_H\r
-\r
-#include <PiDxe.h>\r
-\r
-#include "XPressRich3.h"\r
-\r
-#include <IndustryStandard/Pci.h>\r
-#include <IndustryStandard/Acpi.h>\r
-\r
-#include <Library/BaseLib.h>\r
-#include <Library/BaseMemoryLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/DxeServicesTableLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/MemoryAllocationLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <Library/UefiBootServicesTableLib.h>\r
-\r
-#include <Protocol/PciHostBridgeResourceAllocation.h>\r
-#include <Protocol/PciRootBridgeIo.h>\r
-#include <Protocol/PciIo.h>\r
-#include <Protocol/DevicePath.h>\r
-#include <Protocol/CpuIo2.h>\r
-#include <Protocol/Metronome.h>\r
-\r
-#define PCI_TRACE(txt) DEBUG((EFI_D_VERBOSE, "ARM_PCI: " txt "\n"))\r
-\r
-#define PCIE_ROOTPORT_WRITE32(Add, Val) { UINT32 Value = (UINT32)(Val); CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieRootPortBaseAddress)+(Add)),1,&Value); }\r
-#define PCIE_ROOTPORT_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieRootPortBaseAddress)+(Add)),1,&Val); }\r
-\r
-#define PCIE_CONTROL_WRITE32(Add, Val) { UINT32 Value = (UINT32)(Val); CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieControlBaseAddress)+(Add)),1,&Value); }\r
-#define PCIE_CONTROL_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieControlBaseAddress)+(Add)),1,&Val); }\r
-\r
-/**\r
- * PCI Root Bridge Device Path (ACPI Device Node + End Node)\r
- */\r
-typedef struct {\r
- ACPI_HID_DEVICE_PATH Acpi;\r
- EFI_DEVICE_PATH_PROTOCOL End;\r
-} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;\r
-\r
-typedef enum {\r
- ResTypeIo = 0,\r
- ResTypeMem32,\r
- ResTypePMem32,\r
- ResTypeMem64,\r
- ResTypePMem64,\r
- ResTypeMax\r
-} PCI_RESOURCE_TYPE;\r
-\r
-#define ACPI_SPECFLAG_PREFETCHABLE 0x06\r
-#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL\r
-#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL\r
-\r
-typedef struct {\r
- UINT64 Base;\r
- UINT64 Length;\r
- UINT64 Alignment;\r
-} PCI_RESOURCE_ALLOC;\r
-\r
-typedef struct _PCI_HOST_BRIDGE_INSTANCE PCI_HOST_BRIDGE_INSTANCE;\r
-\r
-/**\r
- * PCI Root Bridge Instance structure\r
- **/\r
-typedef struct {\r
- UINTN Signature;\r
- EFI_HANDLE Handle;\r
- PCI_HOST_BRIDGE_INSTANCE *HostBridge;\r
- //\r
- // Set Type of memory allocation (could be EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM\r
- // and EFI_PCI_HOST_BRIDGE_MEM64_DECODE).\r
- //\r
- UINT64 MemAllocAttributes;\r
- PCI_RESOURCE_ALLOC ResAlloc[ResTypeMax];\r
- UINTN BusStart;\r
- UINTN BusLength;\r
- UINT64 Supports;\r
- UINT64 Attributes;\r
- EFI_PCI_ROOT_BRIDGE_DEVICE_PATH DevicePath;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;\r
-} PCI_ROOT_BRIDGE_INSTANCE;\r
-\r
-/**\r
- * PCI Host Bridge Instance structure\r
- **/\r
-struct _PCI_HOST_BRIDGE_INSTANCE {\r
- UINTN Signature;\r
- EFI_HANDLE Handle;\r
- EFI_HANDLE ImageHandle;\r
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r
- //\r
- // The enumeration cannot be restarted after the process goes into the non initial\r
- // enumeration phase.\r
- //\r
- BOOLEAN CanRestarted;\r
- EFI_CPU_IO2_PROTOCOL *CpuIo;\r
- EFI_METRONOME_ARCH_PROTOCOL *Metronome;\r
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc;\r
-};\r
-\r
-#define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32 ('e', 'h', 's', 't')\r
-#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('e', '2', 'p', 'b')\r
-#define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) CR (a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)\r
-#define INSTANCE_FROM_ROOT_BRIDGE_IO_THIS(a) CR (a, PCI_ROOT_BRIDGE_INSTANCE, Io, PCI_ROOT_BRIDGE_SIGNATURE)\r
-\r
-/**\r
- * PCI Host Bridge Resource Allocator Functions\r
- **/\r
-EFI_STATUS PciHbRaNotifyPhase (\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase\r
- );\r
-\r
-EFI_STATUS PciHbRaGetNextRootBridge (\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN OUT EFI_HANDLE *RootBridgeHandle\r
- );\r
-\r
-EFI_STATUS PciHbRaGetAllocAttributes (\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- OUT UINT64 *Attributes\r
- );\r
-\r
-EFI_STATUS PciHbRaStartBusEnumeration (\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- OUT VOID **Configuration\r
- );\r
-\r
-EFI_STATUS PciHbRaSetBusNumbers (\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- IN VOID *Configuration\r
- );\r
-\r
-EFI_STATUS PciHbRaSubmitResources (\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- IN VOID *Configuration\r
- );\r
-\r
-EFI_STATUS PciHbRaGetProposedResources (\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- OUT VOID **Configuration\r
- );\r
-\r
-EFI_STATUS PciHbRaPreprocessController (\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r
- IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase\r
- );\r
-\r
-\r
-/**\r
- * PCI Root Bridge\r
- **/\r
-EFI_STATUS PciRbPollMem (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINT64 Mask,\r
- IN UINT64 Value,\r
- IN UINT64 Delay,\r
- OUT UINT64 *Result\r
- );\r
-\r
-EFI_STATUS PciRbPollIo (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINT64 Mask,\r
- IN UINT64 Value,\r
- IN UINT64 Delay,\r
- OUT UINT64 *Result\r
- );\r
-\r
-EFI_STATUS PciRbMemRead (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
- );\r
-\r
-EFI_STATUS PciRbMemWrite (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
- );\r
-\r
-EFI_STATUS PciRbIoRead (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
- );\r
-\r
-EFI_STATUS PciRbIoWrite (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
- );\r
-\r
-EFI_STATUS PciRbPciRead (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
- );\r
-\r
-EFI_STATUS PciRbPciWrite (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
- );\r
-\r
-EFI_STATUS PciRbCopyMem (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 DestAddress,\r
- IN UINT64 SrcAddress,\r
- IN UINTN Count\r
- );\r
-\r
-EFI_STATUS PciRbMap (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,\r
- IN VOID *HostAddress,\r
- IN OUT UINTN *NumberOfBytes,\r
- OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
- OUT VOID **Mapping\r
- );\r
-\r
-EFI_STATUS PciRbUnMap (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN VOID *Mapping\r
- );\r
-\r
-EFI_STATUS PciRbAllocateBuffer (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN EFI_ALLOCATE_TYPE Type,\r
- IN EFI_MEMORY_TYPE MemoryType,\r
- IN UINTN Pages,\r
- IN OUT VOID **HostAddress,\r
- IN UINT64 Attributes\r
- );\r
-\r
-EFI_STATUS PciRbFreeBuffer (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN UINTN Pages,\r
- IN VOID *HostAddress\r
- );\r
-\r
-EFI_STATUS PciRbFlush (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This\r
- );\r
-\r
-EFI_STATUS PciRbSetAttributes (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- IN UINT64 Attributes,\r
- IN OUT UINT64 *ResourceBase,\r
- IN OUT UINT64 *ResourceLength\r
- );\r
-\r
-EFI_STATUS PciRbGetAttributes (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- OUT UINT64 *Supports,\r
- OUT UINT64 *Attributes\r
- );\r
-\r
-EFI_STATUS PciRbConfiguration (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
- OUT VOID **Resources\r
- );\r
-\r
-/**\r
- * PCI Root Bridge Functions\r
- **/\r
-EFI_STATUS\r
-PciRbConstructor (\r
- IN PCI_HOST_BRIDGE_INSTANCE *HostBridge,\r
- IN UINT32 PciAcpiUid,\r
- IN UINT64 MemAllocAttributes\r
- );\r
-\r
-EFI_STATUS\r
-PciRbDestructor (\r
- IN PCI_ROOT_BRIDGE_INSTANCE* RootBridge\r
- );\r
-\r
-EFI_STATUS\r
-HWPciRbInit (\r
- IN EFI_CPU_IO2_PROTOCOL *CpuIo\r
- );\r
-\r
-#endif\r
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