Do not create boot option for logical block io device.

[mirror_edk2.git] / ArmPlatformPkg / ArmPlatformPkg.dec

diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec
index 65b4977fdbcd07c3fa36240a159f3d7a196d7cc9..26f84180877bf5c4c7bec2ff2d56dd6a621a8c55 100644 (file)
--- a/ArmPlatformPkg/ArmPlatformPkg.dec
+++ b/ArmPlatformPkg/ArmPlatformPkg.dec
@@ -1,6 +1,6 @@
 #/** @file\r
 #\r
-#  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+#  Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
 #  \r
 #  This program and the accompanying materials                          \r
 #  are licensed and made available under the terms and conditions of the BSD License         \r
@@ -37,6 +37,13 @@
   #\r
   gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }\r
 \r
+  ## Include/Guid/ArmGlobalVariableHob.h\r
+  gArmGlobalVariableGuid      = { 0xc3253c90, 0xa24f, 0x4599, { 0xa6, 0x64, 0x1f, 0x88, 0x13, 0x77, 0x8f, 0xc9} }\r
+\r
+[Ppis]\r
+  ## Include/Ppi/ArmGlobalVariable.h\r
+  gArmGlobalVariablePpiGuid = { 0xab1c1816, 0xd542, 0x4e6f, {0x9b, 0x1e, 0x8e, 0xcd, 0x92, 0x53, 0xe2, 0xe7} }\r
+\r
 [PcdsFeatureFlag.common]\r
   # Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.\r
   gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012\r
@@ -45,23 +52,25 @@
   gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|FALSE|BOOLEAN|0x00000002\r
   gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004\r
 \r
+  gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C\r
+\r
+  # Disable the GOP controller on ExitBootServices(). By default the value is FALSE,\r
+  # we assume the OS will handle the FrameBuffer from the UEFI GOP information.\r
+  gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D\r
+\r
 [PcdsFixedAtBuild.common]\r
-  # These PCDs should be FeaturePcds. But we used these PCDs as an '#if' in an ASM file.\r
-  # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.\r
-  gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|0|UINT32|0x00000003\r
-  gArmPlatformTokenSpaceGuid.PcdMPCoreMaxCores|1|UINT32|0x0000002D\r
-  \r
+  gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039\r
+  gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038\r
+    \r
   # Stack for CPU Cores in Secure Mode\r
   gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000005\r
-  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize|0|UINT32|0x00000006\r
-\r
-  # Stack for CPU Cores in Secure Monitor Mode\r
-  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007\r
-  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0|UINT32|0x00000008\r
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036\r
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006\r
 \r
   # Stack for CPU Cores in Non Secure Mode\r
-  gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0|UINT32|0x00000009\r
-  gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0|UINT32|0x0000000A\r
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT32|0x00000009\r
+  gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037\r
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A\r
     \r
   # Size of the region used by UEFI in permanent memory (Reserved 128MB by default)\r
   gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015\r
@@ -74,6 +83,12 @@
   gArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset|0x0|UINT32|0x00000017\r
   gArmPlatformTokenSpaceGuid.PcdHobListPtrGlobalOffset|0x0|UINT32|0x00000018\r
 \r
+  # Size to reserve in the primary core stack for SEC Global Variables\r
+  gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize|0x0|UINT32|0x00000031\r
+\r
+  # Boot Monitor FileSystem\r
+  gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L""|VOID*|0x0000003A\r
+\r
   #\r
   # ARM Primecells\r
   #\r
@@ -90,8 +105,9 @@
   gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021\r
 \r
   ## PL011 UART\r
-  gArmPlatformTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0x00000000|UINT32|0x0000001F\r
-  gArmPlatformTokenSpaceGuid.PcdUartDefaultTimeout|0x00000000|UINT32|0x00000020\r
+  gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F\r
+  gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020\r
+  gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D\r
 \r
   ## PL031 RealTimeClock\r
   gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024\r
@@ -100,7 +116,7 @@
   ## PL061 GPIO\r
   gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025\r
   \r
-  ## PL111 Lcd\r
+  ## PL111 Lcd & HdLcd\r
   gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026\r
   gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027\r
   \r
@@ -115,7 +131,7 @@
   gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C\r
   gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D\r
   gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L""|VOID*|0x0000000E\r
-  gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|""|VOID*|0x000000F\r
+  gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L""|VOID*|0x000000F\r
   # PcdDefaultBootType define the type of the binary pointed by PcdDefaultBootDevicePath: \r
   #  - 0 = an EFI application\r
   #  - 1 = a Linux kernel with ATAG support\r
@@ -129,4 +145,16 @@
   \r
   gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B\r
   gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C\r
-  \r
+\r
+[PcdsFixedAtBuild.ARM]\r
+  # Stack for CPU Cores in Secure Monitor Mode\r
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007\r
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008\r
+\r
+[PcdsFixedAtBuild.AARCH64]\r
+  # The Secure World is only running in EL3. Only one set of stacks is needed for AArch64.\r
+  # The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize\r
+  # and PcdCPUCoreSecSecondaryStackSize\r
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007\r
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008\r
+\r