#/** @file\r
#\r
-# Copyright (c) 2011-2016, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011-2017, ARM Limited. All rights reserved.\r
# Copyright (c) 2015, Intel Corporation. All rights reserved.\r
#\r
# This program and the accompanying materials\r
gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020\r
gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D\r
gArmPlatformTokenSpaceGuid.PL011UartInterrupt|0x00000000|UINT32|0x0000002F\r
+ gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant|0|UINT8|0x0000003E\r
\r
## PL011 Serial Debug UART\r
gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x00000000|UINT64|0x00000030\r
gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024\r
gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022\r
\r
+ gArmPlatformTokenSpaceGuid.PcdWatchdogCount|0x0|UINT32|0x00000033\r
+\r
[PcdsFixedAtBuild.ARM]\r
# Stack for CPU Cores in Secure Monitor Mode\r
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007\r