#define ARM_VE_SMB_PERIPH_SZ SIZE_64MB\r
\r
// DRAM\r
-#define ARM_VE_DRAM_BASE 0x60000000\r
-#define ARM_VE_DRAM_SZ 0x40000000\r
+#define ARM_VE_DRAM_BASE PcdGet64 (PcdSystemMemoryBase)\r
+#define ARM_VE_DRAM_SZ PcdGet64 (PcdSystemMemorySize)\r
// Inside the DRAM we allocate a section for the VRAM (Video RAM)\r
-#define LCD_VRAM_CORE_TILE_BASE 0x64000000\r
+#define LCD_VRAM_CORE_TILE_BASE 0x64000000\r
\r
// External AXI between daughterboards (Logic Tile)\r
#define ARM_VE_EXT_AXI_BASE 0xE0000000\r
\r
// PL111 Colour LCD Controller - core tile\r
#define PL111_CLCD_CORE_TILE_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x20000)\r
+#define PL111_CLCD_SITE ARM_VE_DAUGHTERBOARD_1_SITE\r
\r
// PL341 Dynamic Memory Controller Base\r
#define ARM_VE_DMC_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE0000)\r
#define ARM_VE_SMC_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE1000)\r
\r
// System Configuration Controller register Base addresses\r
-//#define ARM_VE_SYS_CFG_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE2000)\r
+#define ARM_VE_SYS_CFG_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE2000)\r
+#define ARM_VE_SCC_BASE ARM_VE_SYS_CFG_CTRL_BASE\r
#define ARM_VE_SYS_CFGRW0_REG (ARM_VE_BOARD_PERIPH_BASE + 0xE2000)\r
#define ARM_VE_SYS_CFGRW1_REG (ARM_VE_BOARD_PERIPH_BASE + 0xE2004)\r
#define ARM_VE_SYS_CFGRW2_REG (ARM_VE_BOARD_PERIPH_BASE + 0xE2008)\r
\r
-#define ARM_PLATFORM_SCC_BASE ARM_VE_SYS_CFGRW0_REG\r
-\r
// SP805 Watchdog on Cortex A9 core tile\r
#define SP805_WDOG_CORE_TILE_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE5000)\r
\r
// PL310 L2x0 Cache Controller Base Address\r
//#define ARM_VE_L2x0_CTLR_BASE 0x1E00A000\r
\r
-/***********************************************************************************\r
- Select between Motherboard and Core Tile peripherals\r
-************************************************************************************/\r
-\r
-// Specify which PL111 to use\r
-//#define PL111_CLCD_BASE PL111_CLCD_MOTHERBOARD_BASE\r
-#define PL111_CLCD_BASE PL111_CLCD_CORE_TILE_BASE\r
-\r
-// Specify which Watchdog to use\r
-#define SP805_WDOG_BASE SP805_WDOG_MOTHERBOARD_BASE\r
-//#define SP805_WDOG_BASE SP805_WDOG_CORE_TILE_BASE\r
-\r
/***********************************************************************************\r
Peripherals' misc settings\r
************************************************************************************/\r
#define ARM_VE_DECPROT_BIT_NMC_TZASC_LOCK (1 << 4)\r
#define ARM_VE_DECPROT_BIT_SMC_TZASC_LOCK (1 << 5)\r
\r
-// PL031 RTC - Other settings\r
-#define PL031_PPM_ACCURACY 300000000\r
-\r
-// SP805 Watchdog - Other settings\r
-#define SP805_CLOCK_FREQUENCY 32000\r
-#define SP805_MAX_TICKS 0xFFFFFFFF\r
-\r
-// PL111 Lcd\r
-#define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1\r
-\r
-/***********************************************************************************\r
-// EFI Memory Map in Permanent Memory (DRAM)\r
-************************************************************************************/\r
-\r
-// This region is allocated at the bottom of the DRAM. It will be used\r
-// for fixed address allocations such as Vector Table\r
-#define ARM_VE_EFI_FIX_ADDRESS_REGION_SZ SIZE_8MB\r
-\r
-// This region is the memory declared to PEI as permanent memory for PEI\r
-// and DXE. EFI stacks and heaps will be declared in this region.\r
-#define ARM_VE_EFI_MEMORY_REGION_SZ SIZE_256MB\r
-\r
#endif\r