/** @file\r
* Header defining Versatile Express constants (Base addresses, sizes, flags)\r
*\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
// Can not access the battery backed-up hardware clock on the Versatile Express motherboard\r
#define SYS_CFG_RTC VIRTUAL_SYS_CFG(ARM_VE_UNSUPPORTED,1)\r
\r
+//\r
+// System ID\r
+//\r
+// All RTSM VE models have the same System ID : 0x225F500\r
+//\r
+// FVP models have a different System ID.\r
+// Default Base model System ID : 0x00201100\r
+// [31:28] Rev - Board revision: 0x0 = Rev A\r
+// [27:16] HBI - HBI board number in BCD: 0x020 = v8 Base Platform\r
+// [15:12] Variant - Build variant of board: 0x1 = Variant B. (GIC 64k map)\r
+// [11:8] Plat - Platform type: 0x1 = Model\r
+// [7:0] FPGA - FPGA build, BCD coded: 0x00\r
+//\r
+//HBI = 010 = Foundation Model\r
+//HBI = 020 = Base Platform\r
+//\r
+// And specifically, the GIC register banks start at the following\r
+// addresses:\r
+// Variant = 0 Variant = 1\r
+//GICD 0x2c001000 0x2f000000\r
+//GICC 0x2c002000 0x2c000000\r
+//GICH 0x2c004000 0x2c010000\r
+//GICV 0x2c006000 0x2c020000\r
+\r
+// The default SYS_IDs. These can be changed when starting the model.\r
+#define ARM_RTSM_SYS_ID (0x225F500)\r
+#define ARM_FVP_BASE_SYS_ID (0x00201100)\r
+#define ARM_FVP_FOUNDATION_SYS_ID (0x00101100)\r
+\r
+#define ARM_FVP_SYS_ID_VARIANT_MASK (UINT32)(0xFUL << 12)\r
+\r
#endif /* VEXPRESSMOTHERBOARD_H_ */\r