ArmPkg/PL34xDmc: Remove magic values in PL310L2Cache and clean the code

[mirror_edk2.git] / ArmPlatformPkg / ArmVExpressPkg / Library / ArmVExpressLibCTA9x4 / CTA9x4.c

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c
index b8d1ff0f722f33330c83e3b0a5ae4b1d888ff1c4..c2783bbca27a964a5e473e1557f0596030d7a2c7 100644 (file)
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c
@@ -25,31 +25,38 @@
 #define SerialPrint(txt)  SerialPortWrite (txt, AsciiStrLen(txt)+1);
 
 // DDR2 timings
-struct pl341_dmc_config ddr_timings = {
-    .base              = ARM_VE_DMC_BASE,
-    .has_qos           = 1,
-    .refresh_prd       = 0x3D0,
-    .cas_latency       = 0x8,
-    .write_latency     = 0x3,
-    .t_mrd             = 0x2,
-    .t_ras             = 0xA,
-    .t_rc              = 0xE,
-    .t_rcd             = 0x104,
-    .t_rfc             = 0x2f32,
-    .t_rp              = 0x14,
-    .t_rrd             = 0x2,
-    .t_wr              = 0x4,
-    .t_wtr             = 0x2,
-    .t_xp              = 0x2,
-    .t_xsr             = 0xC8,
-    .t_esr             = 0x14,
-    .memory_cfg                = DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 | DMC_MEMORY_CONFIG_BURST_4 |
-                          DMC_MEMORY_CONFIG_ROW_ADDRESS_15 | DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10,
-    .memory_cfg2       = DMC_MEMORY_CFG2_DQM_INIT | DMC_MEMORY_CFG2_CKE_INIT |
-                                                 DMC_MEMORY_CFG2_BANK_BITS_3 | DMC_MEMORY_CFG2_MEM_WIDTH_32,
-    .memory_cfg3       = 0x00000001,
-    .chip_cfg0         = 0x00010000,
-    .t_faw             = 0x00000A0D,
+PL341_DMC_CONFIG DDRTimings = {
+  .base   = ARM_VE_DMC_BASE,
+  .phy_ctrl_base  = 0x0,  //There is no DDR2 PHY controller on CTA9 test chip
+  .MaxChip   = 1,
+  .IsUserCfg = TRUE,
+  .User0Cfg = 0x7C924924,
+  .User2Cfg = (TC_UIOLHXC_VALUE << TC_UIOLHNC_SHIFT) | (TC_UIOLHXC_VALUE << TC_UIOLHPC_SHIFT) | (0x1 << TC_UIOHOCT_SHIFT) | (0x1 << TC_UIOHSTOP_SHIFT),
+  .HasQos    = TRUE,
+  .refresh_prd  = 0x3D0,
+  .cas_latency  = 0x8,
+  .write_latency  = 0x3,
+  .t_mrd    = 0x2,
+  .t_ras    = 0xA,
+  .t_rc   = 0xE,
+  .t_rcd    = 0x104,
+  .t_rfc    = 0x2f32,
+  .t_rp   = 0x14,
+  .t_rrd    = 0x2,
+  .t_wr   = 0x4,
+  .t_wtr    = 0x2,
+  .t_xp   = 0x2,
+  .t_xsr    = 0xC8,
+  .t_esr    = 0x14,
+  .MemoryCfg   = DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 | DMC_MEMORY_CONFIG_BURST_4 |
+                        DMC_MEMORY_CONFIG_ROW_ADDRESS_15 | DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10,
+  .MemoryCfg2  = DMC_MEMORY_CFG2_DQM_INIT | DMC_MEMORY_CFG2_CKE_INIT |
+            DMC_MEMORY_CFG2_BANK_BITS_3 | DMC_MEMORY_CFG2_MEM_WIDTH_32,
+  .MemoryCfg3  = 0x00000001,
+  .ChipCfg0    = 0x00010000,
+  .t_faw    = 0x00000A0D,
+  .ModeReg = DDR2_MR_BURST_LENGTH_4 | DDR2_MR_CAS_LATENCY_4 | DDR2_MR_WR_CYCLES_4,
+  .ExtModeReg = DDR_EMR_RTT_50R | (DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK),
 };
 
 /**
@@ -219,6 +226,6 @@ ArmPlatformInitializeSystemMemory (
   VOID
   )
 {
-  PL341DmcInit(&ddr_timings);
+  PL341DmcInit(&DDRTimings);
   PL301AxiInit(ARM_VE_FAXI_BASE);
 }