-/** @file
-*
-* Copyright (c) 2011, ARM Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Library/IoLib.h>
-#include <Library/ArmPlatformLib.h>
-#include <Library/DebugLib.h>
-#include <Library/PcdLib.h>
-
-#include <Drivers/SP804Timer.h>
-
-#include <Ppi/ArmMpCoreInfo.h>
-
-#include <ArmPlatform.h>
-
-ARM_CORE_INFO mVersatileExpressMpCoreInfoTable[] = {
- {
- // Cluster 0, Core 0
- 0x0, 0x0,
-
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
- (UINT64)0xFFFFFFFF
- },
- {
- // Cluster 0, Core 1
- 0x0, 0x1,
-
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
- (UINT64)0xFFFFFFFF
- },
- {
- // Cluster 0, Core 2
- 0x0, 0x2,
-
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
- (UINT64)0xFFFFFFFF
- },
- {
- // Cluster 0, Core 3
- 0x0, 0x3,
-
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
- (UINT64)0xFFFFFFFF
- }
-};
-
-/**
- Return if Trustzone is supported by your platform
-
- A non-zero value must be returned if you want to support a Secure World on your platform.
- ArmVExpressTrustzoneInit() will later set up the secure regions.
- This function can return 0 even if Trustzone is supported by your processor. In this case,
- the platform will continue to run in Secure World.
-
- @return A non-zero value if Trustzone supported.
-
-**/
-UINTN
-ArmPlatformTrustzoneSupported (
- VOID
- )
-{
- // Not supported yet but model does have Secure SRAM (but no TZPC/TZASC) so we could support it
- return FALSE;
-}
-
-/**
- Return the current Boot Mode
-
- This function returns the boot reason on the platform
-
- @return Return the current Boot Mode of the platform
-
-**/
-EFI_BOOT_MODE
-ArmPlatformGetBootMode (
- VOID
- )
-{
- return BOOT_WITH_FULL_CONFIGURATION;
-}
-
-/**
- Remap the memory at 0x0
-
- Some platform requires or gives the ability to remap the memory at the address 0x0.
- This function can do nothing if this feature is not relevant to your platform.
-
-**/
-VOID
-ArmPlatformBootRemapping (
- VOID
- )
-{
- // Disable memory remapping and return to normal mapping
- MmioOr32 (SP810_CTRL_BASE, BIT8);
-}
-
-/**
- Initialize controllers that must setup in the normal world
-
- This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
- in the PEI phase.
-
-**/
-VOID
-ArmPlatformNormalInitialize (
- VOID
- )
-{
- // Nothing to do here
-}
-
-/**
- Initialize the system (or sometimes called permanent) memory
-
- This memory is generally represented by the DRAM.
-
-**/
-VOID
-ArmPlatformInitializeSystemMemory (
- VOID
- )
-{
- // Configure periodic timer (TIMER0) for 1MHz operation
- MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
- // Configure 1MHz clock
- MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);
- // configure SP810 to use 1MHz clock and disable
- MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
- // Configure SP810 to use 1MHz clock and disable
- MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
-}
-
-EFI_STATUS
-PrePeiCoreGetMpCoreInfo (
- OUT UINTN *CoreCount,
- OUT ARM_CORE_INFO **ArmCoreTable
- )
-{
- UINT32 ProcType;
-
- ProcType = MmioRead32 (ARM_VE_SYS_PROCID0_REG) & ARM_VE_SYS_PROC_ID_MASK;
- if (ProcType == ARM_VE_SYS_PROC_ID_CORTEX_A9) {
- // Only support one cluster
- *CoreCount = ArmGetCpuCountPerCluster ();
- *ArmCoreTable = mVersatileExpressMpCoreInfoTable;
- return EFI_SUCCESS;
- } else {
- return EFI_UNSUPPORTED;
- }
-}
-
-// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
-EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
-ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
-
-EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
- {
- EFI_PEI_PPI_DESCRIPTOR_PPI,
- &mArmMpCoreInfoPpiGuid,
- &mMpCoreInfoPpi
- }
-};
-
-VOID
-ArmPlatformGetPlatformPpiList (
- OUT UINTN *PpiListSize,
- OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
- )
-{
- *PpiListSize = sizeof(gPlatformPpiTable);
- *PpiList = gPlatformPpiTable;
-}
+/** @file\r
+*\r
+* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#include <Library/IoLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+#include <Ppi/ArmMpCoreInfo.h>\r
+\r
+#include <ArmPlatform.h>\r
+\r
+/**\r
+ Return the core per cluster. The method may differ per core type\r
+\r
+ This function might be called from assembler before any stack is set.\r
+\r
+ @return Return the core count per cluster\r
+\r
+**/\r
+UINTN\r
+ArmGetCpuCountPerCluster (\r
+ VOID\r
+ );\r
+\r
+ARM_CORE_INFO mVersatileExpressMpCoreInfoTable[] = {\r
+ {\r
+ // Cluster 0, Core 0\r
+ 0x0, 0x0,\r
+\r
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
+ (UINT64)0xFFFFFFFF\r
+ },\r
+ {\r
+ // Cluster 0, Core 1\r
+ 0x0, 0x1,\r
+\r
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
+ (UINT64)0xFFFFFFFF\r
+ },\r
+ {\r
+ // Cluster 0, Core 2\r
+ 0x0, 0x2,\r
+\r
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
+ (UINT64)0xFFFFFFFF\r
+ },\r
+ {\r
+ // Cluster 0, Core 3\r
+ 0x0, 0x3,\r
+\r
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
+ (UINT64)0xFFFFFFFF\r
+ },\r
+ {\r
+ // Cluster 1, Core 0\r
+ 0x1, 0x0,\r
+\r
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
+ (UINT64)0xFFFFFFFF\r
+ },\r
+ {\r
+ // Cluster 1, Core 1\r
+ 0x1, 0x1,\r
+\r
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
+ (UINT64)0xFFFFFFFF\r
+ },\r
+ {\r
+ // Cluster 1, Core 2\r
+ 0x1, 0x2,\r
+\r
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
+ (UINT64)0xFFFFFFFF\r
+ },\r
+ {\r
+ // Cluster 1, Core 3\r
+ 0x1, 0x3,\r
+\r
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
+ (UINT64)0xFFFFFFFF\r
+ }\r
+};\r
+\r
+/**\r
+ Return the current Boot Mode\r
+\r
+ This function returns the boot reason on the platform\r
+\r
+ @return Return the current Boot Mode of the platform\r
+\r
+**/\r
+EFI_BOOT_MODE\r
+ArmPlatformGetBootMode (\r
+ VOID\r
+ )\r
+{\r
+ return BOOT_WITH_FULL_CONFIGURATION;\r
+}\r
+\r
+/**\r
+ Initialize controllers that must setup in the normal world\r
+\r
+ This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim\r
+ in the PEI phase.\r
+\r
+**/\r
+RETURN_STATUS\r
+ArmPlatformInitialize (\r
+ IN UINTN MpId\r
+ )\r
+{\r
+ if (!ArmPlatformIsPrimaryCore (MpId)) {\r
+ return RETURN_SUCCESS;\r
+ }\r
+\r
+ // Disable memory remapping and return to normal mapping\r
+ MmioOr32 (SP810_CTRL_BASE, BIT8);\r
+\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+ Initialize the system (or sometimes called permanent) memory\r
+\r
+ This memory is generally represented by the DRAM.\r
+\r
+**/\r
+VOID\r
+ArmPlatformInitializeSystemMemory (\r
+ VOID\r
+ )\r
+{\r
+ // Nothing to do here\r
+}\r
+\r
+EFI_STATUS\r
+PrePeiCoreGetMpCoreInfo (\r
+ OUT UINTN *CoreCount,\r
+ OUT ARM_CORE_INFO **ArmCoreTable\r
+ )\r
+{\r
+ UINT32 ProcType;\r
+\r
+ ProcType = MmioRead32 (ARM_VE_SYS_PROCID0_REG) & ARM_VE_SYS_PROC_ID_MASK;\r
+ if ((ProcType == ARM_VE_SYS_PROC_ID_CORTEX_A9) || (ProcType == ARM_VE_SYS_PROC_ID_CORTEX_A15)) {\r
+ // Only support one cluster on all but ARMv8 FVP platform. FVP still uses CortexA9 ID.\r
+ *CoreCount = ArmGetCpuCountPerCluster ();\r
+ *ArmCoreTable = mVersatileExpressMpCoreInfoTable;\r
+ return EFI_SUCCESS;\r
+ } else {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+}\r
+\r
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };\r
+\r
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {\r
+ {\r
+ EFI_PEI_PPI_DESCRIPTOR_PPI,\r
+ &gArmMpCoreInfoPpiGuid,\r
+ &mMpCoreInfoPpi\r
+ }\r
+};\r
+\r
+VOID\r
+ArmPlatformGetPlatformPpiList (\r
+ OUT UINTN *PpiListSize,\r
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList\r
+ )\r
+{\r
+ *PpiListSize = sizeof(gPlatformPpiTable);\r
+ *PpiList = gPlatformPpiTable;\r
+}\r
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