ArmPlatformPkg/TZASC: Allow specifying subregions to be disabled

[mirror_edk2.git] / ArmPlatformPkg / ArmVExpressPkg / Library / ArmVExpressSecLibCTA9x4 / CTA9x4Sec.c

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibCTA9x4/CTA9x4Sec.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibCTA9x4/CTA9x4Sec.c
index 6fa0774f59f8cb8356825356c670c3723cde9b7f..42d731ea98c9ea99dd3b17168ad698023b86ef8b 100644 (file)
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibCTA9x4/CTA9x4Sec.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibCTA9x4/CTA9x4Sec.c
@@ -72,18 +72,18 @@ ArmPlatformSecTrustzoneInit (
   // NOR Flash 0 non secure (BootMon)\r
   TZASCSetRegion(ARM_VE_TZASC_BASE,1,TZASC_REGION_ENABLED,\r
       ARM_VE_SMB_NOR0_BASE,0,\r
-      TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW);\r
+      TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW, 0);\r
 \r
   // NOR Flash 1. The first half of the NOR Flash1 must be secure for the secure firmware (sec_uefi.bin)\r
   if (PcdGetBool (PcdTrustzoneSupport) == TRUE) {\r
     //Note: Your OS Kernel must be aware of the secure regions before to enable this region\r
     TZASCSetRegion(ARM_VE_TZASC_BASE,2,TZASC_REGION_ENABLED,\r
         ARM_VE_SMB_NOR1_BASE + SIZE_32MB,0,\r
-        TZASC_REGION_SIZE_32MB, TZASC_REGION_SECURITY_NSRW);\r
+        TZASC_REGION_SIZE_32MB, TZASC_REGION_SECURITY_NSRW, 0);\r
   } else {\r
     TZASCSetRegion(ARM_VE_TZASC_BASE,2,TZASC_REGION_ENABLED,\r
         ARM_VE_SMB_NOR1_BASE,0,\r
-        TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW);\r
+        TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW, 0);\r
   }\r
 \r
   // Base of SRAM. Only half of SRAM in Non Secure world\r
@@ -92,22 +92,22 @@ ArmPlatformSecTrustzoneInit (
     //Note: Your OS Kernel must be aware of the secure regions before to enable this region\r
     TZASCSetRegion(ARM_VE_TZASC_BASE,3,TZASC_REGION_ENABLED,\r
         ARM_VE_SMB_SRAM_BASE,0,\r
-        TZASC_REGION_SIZE_16MB, TZASC_REGION_SECURITY_NSRW);\r
+        TZASC_REGION_SIZE_16MB, TZASC_REGION_SECURITY_NSRW, 0);\r
   } else {\r
     TZASCSetRegion(ARM_VE_TZASC_BASE,3,TZASC_REGION_ENABLED,\r
         ARM_VE_SMB_SRAM_BASE,0,\r
-        TZASC_REGION_SIZE_32MB, TZASC_REGION_SECURITY_NSRW);\r
+        TZASC_REGION_SIZE_32MB, TZASC_REGION_SECURITY_NSRW, 0);\r
   }\r
 \r
   // Memory Mapped Peripherals. All in non secure world\r
   TZASCSetRegion(ARM_VE_TZASC_BASE,4,TZASC_REGION_ENABLED,\r
       ARM_VE_SMB_PERIPH_BASE,0,\r
-      TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW);\r
+      TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW, 0);\r
 \r
   // MotherBoard Peripherals and On-chip peripherals.\r
   TZASCSetRegion(ARM_VE_TZASC_BASE,5,TZASC_REGION_ENABLED,\r
       ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE,0,\r
-      TZASC_REGION_SIZE_256MB, TZASC_REGION_SECURITY_NSRW);\r
+      TZASC_REGION_SIZE_256MB, TZASC_REGION_SECURITY_NSRW, 0);\r
 }\r
 \r
 /**\r