-/*
- * boot.S - simple register setup code for junping to a second stage bootloader
- *
- * Copyright (C) 2011-2013 ARM Limited.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of ARM nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
- * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
- * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
- * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * This license can also be found in the LICENSE.TXT file.
- */
-
- .text
-
- .globl _start
-
-.set LED_ADDR, 0x1c010008
-
-_start:
- /*
- * EL3 initialisation
- */
-
- // Set LED to show progress.
- ldr x1, =LED_ADDR
- mov w0, #0x1
- str w0, [x1]
- dsb sy
-
-#if defined START_EL2
-
- mrs x0, CurrentEL
- cmp x0, #0xc // EL3?
- b.ne start_ns // skip EL3 initialisation
-
- mov x0, #0x30 // RES1
- orr x0, x0, #(1 << 0) // Non-secure bit
- orr x0, x0, #(1 << 8) // HVC enable
- orr x0, x0, #(1 << 10) // 64-bit EL2
- msr scr_el3, x0
-
- msr cptr_el3, xzr // Disable copro. traps to EL3
-
- ldr x0, =CNTFRQ
- msr cntfrq_el0, x0
-
- /*
- * Check for the primary CPU to avoid a race on the distributor
- * registers.
- */
- mrs x0, mpidr_el1
- tst x0, #15
- b.ne 1f // secondary CPU
-
- ldr x1, =GIC_DIST_BASE // GICD_CTLR
- mov w0, #3 // EnableGrp0 | EnableGrp1
- str w0, [x1]
-
-1: ldr x1, =GIC_DIST_BASE + 0x80 // GICD_IGROUPR
- mov w0, #~0 // Grp1 interrupts
- str w0, [x1], #4
- b.ne 2f // Only local interrupts for secondary CPUs
- str w0, [x1], #4
- str w0, [x1], #4
-
-2: ldr x1, =GIC_CPU_BASE // GICC_CTLR
- ldr w0, [x1]
- orr w0, w0, #3 // EnableGrp0 | EnableGrp1
- str w0, [x1]
-
- mov w0, #1 << 7 // allow NS access to GICC_PMR
- str w0, [x1, #4] // GICC_PMR
-
- msr sctlr_el2, xzr
-
-#if defined START_EL1
-
- /* Now setup our EL1. Controlled by EL2 config on Model */
- mrs x0, hcr_el2 // Read EL2 Hypervisor configuration Register
- orr x0, x0, #(1 << 31) // Set EL1 to be 64bit
-
- // Send all interrupts to their respective Exception levels for EL2
- bic x0, x0, #(1 << 3) // Disable virtual FIQ
- bic x0, x0, #(1 << 4) // Disable virtual IRQ
- bic x0, x0, #(1 << 5) // Disable virtual SError and Abort
- msr hcr_el2, x0 // Write back our settings
-
- /*
- * Enable architected timer access
- */
- mrs x0, cnthctl_el2
- orr x0, x0, #3 // Enable EL1 access to timers
- msr cnthctl_el2, x0
-
- mrs x0, cntkctl_el1
- orr x0, x0, #3 // EL0 access to counters
- msr cntkctl_el1, x0
-
- /* Set ID regs */
- mrs x0, midr_el1
- mrs x1, mpidr_el1
- msr vpidr_el2, x0
- msr vmpidr_el2, x1
-
- /* Coprocessor traps. */
- mov x0, #0x33ff
- msr cptr_el2, x0 // Disable copro. traps to EL2
-
- msr hstr_el2, xzr // Disable CP15 traps to EL2
-
-#endif // START_EL1
-
- /* Configure UART. Primary CPU only */
- mrs x4, mpidr_el1
- tst x4, #15
- b.ne 1f
-
- /*
- * UART initialisation (38400 8N1)
- */
- ldr x4, =UART_BASE // UART base
- mov w5, #0x10 // ibrd
- str w5, [x4, #0x24]
- mov w5, #0xc300
- orr w5, w5, #0x0001 // cr
- str w5, [x4, #0x30]
-
- /*
- * Prepare the switch to the EL2_SP2 mode from EL3
- */
-1: ldr x0, =start_ns // Return after mode switch
-#if defined START_EL1
- mov x1, #0x3c5 // EL1_SP1 | D | A | I | F
-#else
- mov x1, #0x3c9 // EL2_SP2 | D | A | I | F
-#endif
-
- msr elr_el3, x0
- msr spsr_el3, x1
- eret
-
-#endif // START_EL2
-
-
-start_ns:
-
-/*
- * We do not have NOR flash on the Foundation model. So run UEFI from RAM.
- * On the full model we use the NOR FLASH to store UEFI, so start there.
- */
-#if defined FOUNDATION_MODEL
- mov x0, #0xa0000000
-#else
- mov x0, #0x0
-#endif
- br x0
-
- .ltorg
-
- .org 0x200
+/*\r
+ * boot.S - simple register setup code for junping to a second stage bootloader\r
+ *\r
+ * Copyright (C) 2011-2013 ARM Limited.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are\r
+ * met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in\r
+ * the documentation and/or other materials provided with the\r
+ * distribution.\r
+ * * Neither the name of ARM nor the names of its contributors may be\r
+ * used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS\r
+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\r
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\r
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED\r
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\r
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This license can also be found in the LICENSE.TXT file.\r
+ */\r
+\r
+ .text\r
+\r
+ .globl _start\r
+\r
+.set LED_ADDR, 0x1c010008\r
+\r
+_start:\r
+ /*\r
+ * EL3 initialisation\r
+ */\r
+\r
+ // Set LED to show progress.\r
+ ldr x1, =LED_ADDR\r
+ mov w0, #0x1\r
+ str w0, [x1]\r
+ dsb sy\r
+\r
+#if defined START_EL2\r
+\r
+ mrs x0, CurrentEL\r
+ cmp x0, #0xc // EL3?\r
+ b.ne start_ns // skip EL3 initialisation\r
+\r
+ mov x0, #0x30 // RES1\r
+ orr x0, x0, #(1 << 0) // Non-secure bit\r
+ orr x0, x0, #(1 << 8) // HVC enable\r
+ orr x0, x0, #(1 << 10) // 64-bit EL2\r
+ msr scr_el3, x0\r
+\r
+ msr cptr_el3, xzr // Disable copro. traps to EL3\r
+\r
+ ldr x0, =CNTFRQ\r
+ msr cntfrq_el0, x0\r
+\r
+ /*\r
+ * Check for the primary CPU to avoid a race on the distributor\r
+ * registers.\r
+ */\r
+ mrs x0, mpidr_el1\r
+ tst x0, #15\r
+ b.ne 1f // secondary CPU\r
+\r
+ ldr x1, =GIC_DIST_BASE // GICD_CTLR\r
+ mov w0, #3 // EnableGrp0 | EnableGrp1\r
+ str w0, [x1]\r
+\r
+1: ldr x1, =GIC_DIST_BASE + 0x80 // GICD_IGROUPR\r
+ mov w0, #~0 // Grp1 interrupts\r
+ str w0, [x1], #4\r
+ b.ne 2f // Only local interrupts for secondary CPUs\r
+ str w0, [x1], #4\r
+ str w0, [x1], #4\r
+\r
+2: ldr x1, =GIC_CPU_BASE // GICC_CTLR\r
+ ldr w0, [x1]\r
+ orr w0, w0, #3 // EnableGrp0 | EnableGrp1\r
+ str w0, [x1]\r
+\r
+ mov w0, #1 << 7 // allow NS access to GICC_PMR\r
+ str w0, [x1, #4] // GICC_PMR\r
+\r
+ msr sctlr_el2, xzr\r
+\r
+#if defined START_EL1\r
+\r
+ /* Now setup our EL1. Controlled by EL2 config on Model */\r
+ mrs x0, hcr_el2 // Read EL2 Hypervisor configuration Register\r
+ orr x0, x0, #(1 << 31) // Set EL1 to be 64bit\r
+\r
+ // Send all interrupts to their respective Exception levels for EL2\r
+ bic x0, x0, #(1 << 3) // Disable virtual FIQ\r
+ bic x0, x0, #(1 << 4) // Disable virtual IRQ\r
+ bic x0, x0, #(1 << 5) // Disable virtual SError and Abort\r
+ msr hcr_el2, x0 // Write back our settings\r
+\r
+ /*\r
+ * Enable architected timer access\r
+ */\r
+ mrs x0, cnthctl_el2\r
+ orr x0, x0, #3 // Enable EL1 access to timers\r
+ msr cnthctl_el2, x0\r
+\r
+ mrs x0, cntkctl_el1\r
+ orr x0, x0, #3 // EL0 access to counters\r
+ msr cntkctl_el1, x0\r
+\r
+ /* Set ID regs */\r
+ mrs x0, midr_el1\r
+ mrs x1, mpidr_el1\r
+ msr vpidr_el2, x0\r
+ msr vmpidr_el2, x1\r
+\r
+ /* Coprocessor traps. */\r
+ mov x0, #0x33ff\r
+ msr cptr_el2, x0 // Disable copro. traps to EL2\r
+\r
+ msr hstr_el2, xzr // Disable CP15 traps to EL2\r
+\r
+#endif // START_EL1\r
+\r
+ /* Configure UART. Primary CPU only */\r
+ mrs x4, mpidr_el1\r
+ tst x4, #15\r
+ b.ne 1f\r
+\r
+ /*\r
+ * UART initialisation (38400 8N1)\r
+ */\r
+ ldr x4, =UART_BASE // UART base\r
+ mov w5, #0x10 // ibrd\r
+ str w5, [x4, #0x24]\r
+ mov w5, #0xc300\r
+ orr w5, w5, #0x0001 // cr\r
+ str w5, [x4, #0x30]\r
+\r
+ /*\r
+ * Prepare the switch to the EL2_SP2 mode from EL3\r
+ */\r
+1: ldr x0, =start_ns // Return after mode switch\r
+#if defined START_EL1\r
+ mov x1, #0x3c5 // EL1_SP1 | D | A | I | F\r
+#else\r
+ mov x1, #0x3c9 // EL2_SP2 | D | A | I | F\r
+#endif\r
+\r
+ msr elr_el3, x0\r
+ msr spsr_el3, x1\r
+ eret\r
+\r
+#endif // START_EL2\r
+\r
+\r
+start_ns:\r
+\r
+/*\r
+ * We do not have NOR flash on the Foundation model. So run UEFI from RAM.\r
+ * On the full model we use the NOR FLASH to store UEFI, so start there.\r
+ */\r
+#if defined FOUNDATION_MODEL\r
+ mov x0, #0xa0000000\r
+#else\r
+ mov x0, #0x0\r
+#endif\r
+ br x0\r
+\r
+ .ltorg\r
+\r
+ .org 0x200\r
projects / mirror_edk2.git / blobdiff