ArmPlatformPkg: Fix PL011 Glitches.

[mirror_edk2.git] / ArmPlatformPkg / Drivers / PL011Uart / PL011Uart.c

diff --git a/ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.c b/ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.c
index 3c283fdf33e1d64509de262638d4ca82af581161..3748972acbfc80f1077b9b928756a72cc77b5c75 100644 (file)
--- a/ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.c
+++ b/ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.c
@@ -32,6 +32,8 @@ STATIC CONST UINT32 mInvalidControlBits = EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE;
 /**\r
 \r
   Initialise the serial port to the specified settings.\r
+  The serial port is re-configured only if the specified settings\r
+  are different from the current settings.\r
   All unspecified settings will be set to the default values.\r
 \r
   @param  UartBase                The base address of the serial device.\r
@@ -191,6 +193,26 @@ PL011UartInitializePort (
     Integer = Divisor >> FRACTION_PART_SIZE_IN_BITS;\r
     Fractional = Divisor & FRACTION_PART_MASK;\r
   }\r
+\r
+  //\r
+  // If PL011 is already initialized, check the current settings\r
+  // and re-initialize only if the settings are different.\r
+  //\r
+  if (((MmioRead32 (UartBase + UARTCR) & PL011_UARTCR_UARTEN) != 0) &&\r
+       (MmioRead32 (UartBase + UARTLCR_H) == LineControl) &&\r
+       (MmioRead32 (UartBase + UARTIBRD) == Integer) &&\r
+       (MmioRead32 (UartBase + UARTFBRD) == Fractional)) {\r
+    // Nothing to do - already initialized with correct attributes\r
+    return RETURN_SUCCESS;\r
+  }\r
+\r
+  // Wait for the end of transmission\r
+  while ((MmioRead32 (UartBase + UARTFR) & PL011_UARTFR_TXFE) == 0);\r
+\r
+  // Disable UART: "The UARTLCR_H, UARTIBRD, and UARTFBRD registers must not be changed\r
+  // when the UART is enabled"\r
+  MmioWrite32 (UartBase + UARTCR, 0);\r
+\r
   // Set Baud Rate Registers\r
   MmioWrite32 (UartBase + UARTIBRD, Integer);\r
   MmioWrite32 (UartBase + UARTFBRD, Fractional);\r