+++ /dev/null
-/** @file\r
- Header for the MMC Host Protocol implementation for the ARM PrimeCell PL180.\r
-\r
- Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
-**/\r
-\r
-#ifndef __PL180_MCI_H\r
-#define __PL180_MCI_H\r
-\r
-#include <Uefi.h>\r
-\r
-#include <Protocol/MmcHost.h>\r
-\r
-#include <Library/UefiLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/UefiBootServicesTableLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/TimerLib.h>\r
-#include <Library/PcdLib.h>\r
-\r
-#define PL180_MCI_DXE_VERSION 0x10\r
-\r
-#define MCI_SYSCTL FixedPcdGet32 (PcdPL180MciBaseAddress)\r
-\r
-#define MCI_POWER_CONTROL_REG (MCI_SYSCTL + 0x000)\r
-#define MCI_CLOCK_CONTROL_REG (MCI_SYSCTL + 0x004)\r
-#define MCI_ARGUMENT_REG (MCI_SYSCTL + 0x008)\r
-#define MCI_COMMAND_REG (MCI_SYSCTL + 0x00C)\r
-#define MCI_RESPCMD_REG (MCI_SYSCTL + 0x010)\r
-#define MCI_RESPONSE3_REG (MCI_SYSCTL + 0x014)\r
-#define MCI_RESPONSE2_REG (MCI_SYSCTL + 0x018)\r
-#define MCI_RESPONSE1_REG (MCI_SYSCTL + 0x01C)\r
-#define MCI_RESPONSE0_REG (MCI_SYSCTL + 0x020)\r
-#define MCI_DATA_TIMER_REG (MCI_SYSCTL + 0x024)\r
-#define MCI_DATA_LENGTH_REG (MCI_SYSCTL + 0x028)\r
-#define MCI_DATA_CTL_REG (MCI_SYSCTL + 0x02C)\r
-#define MCI_DATA_COUNTER (MCI_SYSCTL + 0x030)\r
-#define MCI_STATUS_REG (MCI_SYSCTL + 0x034)\r
-#define MCI_CLEAR_STATUS_REG (MCI_SYSCTL + 0x038)\r
-#define MCI_INT0_MASK_REG (MCI_SYSCTL + 0x03C)\r
-#define MCI_INT1_MASK_REG (MCI_SYSCTL + 0x040)\r
-#define MCI_SELECT_REG (MCI_SYSCTL + 0x044)\r
-#define MCI_FIFOCOUNT_REG (MCI_SYSCTL + 0x048)\r
-#define MCI_FIFO_REG (MCI_SYSCTL + 0x080)\r
-#define MCI_PERIPH_ID_REG0 (MCI_SYSCTL + 0xFE0)\r
-#define MCI_PERIPH_ID_REG1 (MCI_SYSCTL + 0xFE4)\r
-#define MCI_PERIPH_ID_REG2 (MCI_SYSCTL + 0xFE8)\r
-#define MCI_PERIPH_ID_REG3 (MCI_SYSCTL + 0xFEC)\r
-#define MCI_PCELL_ID_REG0 (MCI_SYSCTL + 0xFF0)\r
-#define MCI_PCELL_ID_REG1 (MCI_SYSCTL + 0xFF4)\r
-#define MCI_PCELL_ID_REG2 (MCI_SYSCTL + 0xFF8)\r
-#define MCI_PCELL_ID_REG3 (MCI_SYSCTL + 0xFFC)\r
-\r
-#define MCI_PERIPH_ID0 0x80\r
-#define MCI_PERIPH_ID1 0x11\r
-#define MCI_PERIPH_ID2 0x04\r
-#define MCI_PERIPH_ID3 0x00\r
-#define MCI_PCELL_ID0 0x0D\r
-#define MCI_PCELL_ID1 0xF0\r
-#define MCI_PCELL_ID2 0x05\r
-#define MCI_PCELL_ID3 0xB1\r
-\r
-#define MCI_POWER_OFF 0\r
-#define MCI_POWER_UP BIT1\r
-#define MCI_POWER_ON (BIT1 | BIT0)\r
-#define MCI_POWER_OPENDRAIN BIT6\r
-#define MCI_POWER_ROD BIT7\r
-\r
-#define MCI_CLOCK_ENABLE BIT8\r
-#define MCI_CLOCK_POWERSAVE BIT9\r
-#define MCI_CLOCK_BYPASS BIT10\r
-#define MCI_CLOCK_WIDEBUS BIT11\r
-\r
-#define MCI_STATUS_CMD_CMDCRCFAIL BIT0\r
-#define MCI_STATUS_CMD_DATACRCFAIL BIT1\r
-#define MCI_STATUS_CMD_CMDTIMEOUT BIT2\r
-#define MCI_STATUS_CMD_DATATIMEOUT BIT3\r
-#define MCI_STATUS_CMD_TX_UNDERRUN BIT4\r
-#define MCI_STATUS_CMD_RXOVERRUN BIT5\r
-#define MCI_STATUS_CMD_RESPEND BIT6\r
-#define MCI_STATUS_CMD_SENT BIT7\r
-#define MCI_STATUS_CMD_DATAEND BIT8\r
-#define MCI_STATUS_CMD_START_BIT_ERROR BIT9\r
-#define MCI_STATUS_CMD_DATABLOCKEND BIT10\r
-#define MCI_STATUS_CMD_ACTIVE BIT11\r
-#define MCI_STATUS_CMD_TXACTIVE BIT12\r
-#define MCI_STATUS_CMD_RXACTIVE BIT13\r
-#define MCI_STATUS_CMD_TXFIFOHALFEMPTY BIT14\r
-#define MCI_STATUS_CMD_RXFIFOHALFFULL BIT15\r
-#define MCI_STATUS_CMD_TXFIFOFULL BIT16\r
-#define MCI_STATUS_CMD_RXFIFOFULL BIT17\r
-#define MCI_STATUS_CMD_TXFIFOEMPTY BIT18\r
-#define MCI_STATUS_CMD_RXFIFOEMPTY BIT19\r
-#define MCI_STATUS_CMD_TXDATAAVAILBL BIT20\r
-#define MCI_STATUS_CMD_RXDATAAVAILBL BIT21\r
-\r
-#define MCI_STATUS_TXDONE (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND)\r
-#define MCI_STATUS_RXDONE (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND)\r
-#define MCI_STATUS_READ_ERROR ( MCI_STATUS_CMD_DATACRCFAIL \\r
- | MCI_STATUS_CMD_DATATIMEOUT \\r
- | MCI_STATUS_CMD_RXOVERRUN \\r
- | MCI_STATUS_CMD_START_BIT_ERROR )\r
-#define MCI_STATUS_WRITE_ERROR ( MCI_STATUS_CMD_DATACRCFAIL \\r
- | MCI_STATUS_CMD_DATATIMEOUT \\r
- | MCI_STATUS_CMD_TX_UNDERRUN )\r
-#define MCI_STATUS_CMD_ERROR ( MCI_STATUS_CMD_CMDCRCFAIL \\r
- | MCI_STATUS_CMD_CMDTIMEOUT \\r
- | MCI_STATUS_CMD_START_BIT_ERROR )\r
-\r
-#define MCI_CLR_CMD_STATUS ( MCI_STATUS_CMD_RESPEND \\r
- | MCI_STATUS_CMD_SENT \\r
- | MCI_STATUS_CMD_ERROR )\r
-\r
-#define MCI_CLR_READ_STATUS ( MCI_STATUS_RXDONE \\r
- | MCI_STATUS_READ_ERROR )\r
-\r
-#define MCI_CLR_WRITE_STATUS ( MCI_STATUS_TXDONE \\r
- | MCI_STATUS_WRITE_ERROR )\r
-\r
-#define MCI_CLR_ALL_STATUS (BIT11 - 1)\r
-\r
-#define MCI_DATACTL_DISABLE_MASK 0xFE\r
-#define MCI_DATACTL_ENABLE BIT0\r
-#define MCI_DATACTL_CONT_TO_CARD 0\r
-#define MCI_DATACTL_CARD_TO_CONT BIT1\r
-#define MCI_DATACTL_BLOCK_TRANS 0\r
-#define MCI_DATACTL_STREAM_TRANS BIT2\r
-#define MCI_DATACTL_DMA_DISABLED 0\r
-#define MCI_DATACTL_DMA_ENABLE BIT3\r
-\r
-#define INDX_MASK 0x3F\r
-\r
-#define MCI_CPSM_WAIT_RESPONSE BIT6\r
-#define MCI_CPSM_LONG_RESPONSE BIT7\r
-#define MCI_CPSM_LONG_INTERRUPT BIT8\r
-#define MCI_CPSM_LONG_PENDING BIT9\r
-#define MCI_CPSM_ENABLE BIT10\r
-\r
-#define MCI_TRACE(txt) DEBUG ((EFI_D_BLKIO, "ARM_MCI: " txt "\n"))\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-MciGetDriverName (\r
- IN EFI_COMPONENT_NAME_PROTOCOL *This,\r
- IN CHAR8 *Language,\r
- OUT CHAR16 **DriverName\r
- );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-MciGetControllerName (\r
- IN EFI_COMPONENT_NAME_PROTOCOL *This,\r
- IN EFI_HANDLE ControllerHandle,\r
- IN EFI_HANDLE ChildHandle OPTIONAL,\r
- IN CHAR8 *Language,\r
- OUT CHAR16 **ControllerName\r
- );\r
-\r
-#endif\r
projects / mirror_edk2.git / blobdiff