UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm

[mirror_edk2.git] / ArmPlatformPkg / Drivers / SP805WatchdogDxe / SP805Watchdog.h

diff --git a/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.h b/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.h
index 4d5e145d8b0bcbddacaf10395f33bb70f355b121..597d6911fa1091c060a2ee231b9de8ba767b0c33 100644 (file)
--- a/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.h
+++ b/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.h
@@ -1,39 +1,32 @@
 /** @file\r
-*\r
-*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-*\r
-*  This program and the accompanying materials\r
-*  are licensed and made available under the terms and conditions of the BSD License\r
-*  which accompanies this distribution.  The full text of the license may be found at\r
-*  http://opensource.org/licenses/bsd-license.php\r
-*\r
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
 \r
+  Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
 \r
 #ifndef __SP805_WATCHDOG_H__\r
 #define __SP805_WATCHDOG_H__\r
 \r
 // SP805 Watchdog Registers\r
-#define SP805_WDOG_LOAD_REG             ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x000)\r
-#define SP805_WDOG_CURRENT_REG          ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x004)\r
-#define SP805_WDOG_CONTROL_REG          ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x008)\r
-#define SP805_WDOG_INT_CLR_REG          ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x00C)\r
-#define SP805_WDOG_RAW_INT_STS_REG      ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x010)\r
-#define SP805_WDOG_MSK_INT_STS_REG      ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x014)\r
-#define SP805_WDOG_LOCK_REG             ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xC00)\r
-\r
-#define SP805_WDOG_PERIPH_ID0           ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE0)\r
-#define SP805_WDOG_PERIPH_ID1           ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE4)\r
-#define SP805_WDOG_PERIPH_ID2           ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE8)\r
-#define SP805_WDOG_PERIPH_ID3           ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFEC)\r
-\r
-#define SP805_WDOG_PCELL_ID0            ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF0)\r
-#define SP805_WDOG_PCELL_ID1            ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF4)\r
-#define SP805_WDOG_PCELL_ID2            ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF8)\r
-#define SP805_WDOG_PCELL_ID3            ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFFC)\r
+#define SP805_WDOG_LOAD_REG         ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x000)\r
+#define SP805_WDOG_CURRENT_REG      ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x004)\r
+#define SP805_WDOG_CONTROL_REG      ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x008)\r
+#define SP805_WDOG_INT_CLR_REG      ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x00C)\r
+#define SP805_WDOG_RAW_INT_STS_REG  ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x010)\r
+#define SP805_WDOG_MSK_INT_STS_REG  ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x014)\r
+#define SP805_WDOG_LOCK_REG         ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xC00)\r
+\r
+#define SP805_WDOG_PERIPH_ID0  ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE0)\r
+#define SP805_WDOG_PERIPH_ID1  ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE4)\r
+#define SP805_WDOG_PERIPH_ID2  ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE8)\r
+#define SP805_WDOG_PERIPH_ID3  ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFEC)\r
+\r
+#define SP805_WDOG_PCELL_ID0  ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF0)\r
+#define SP805_WDOG_PCELL_ID1  ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF4)\r
+#define SP805_WDOG_PCELL_ID2  ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF8)\r
+#define SP805_WDOG_PCELL_ID3  ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFFC)\r
 \r
 // Timer control register bit definitions\r
 #define SP805_WDOG_CTRL_INTEN           BIT0\r
@@ -45,4 +38,4 @@
 #define SP805_WDOG_LOCK_IS_LOCKED       0x00000001\r
 #define SP805_WDOG_SPECIAL_UNLOCK_CODE  0x1ACCE551\r
 \r
-#endif  // __SP805_WATCHDOG_H__\r
+#endif // __SP805_WATCHDOG_H__\r