+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011-2016, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#ifndef __PL011_UART_H__\r
-#define __PL011_UART_H__\r
-\r
-#include <Uefi.h>\r
-#include <Protocol/SerialIo.h>\r
-\r
-#define PL011_VARIANT_ZTE 1\r
-\r
-// PL011 Registers\r
-#if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE\r
-#define UARTDR 0x004\r
-#define UARTRSR 0x010\r
-#define UARTECR 0x010\r
-#define UARTFR 0x014\r
-#define UARTIBRD 0x024\r
-#define UARTFBRD 0x028\r
-#define UARTLCR_H 0x030\r
-#define UARTCR 0x034\r
-#define UARTIFLS 0x038\r
-#define UARTIMSC 0x040\r
-#define UARTRIS 0x044\r
-#define UARTMIS 0x048\r
-#define UARTICR 0x04c\r
-#define UARTDMACR 0x050\r
-#else\r
-#define UARTDR 0x000\r
-#define UARTRSR 0x004\r
-#define UARTECR 0x004\r
-#define UARTFR 0x018\r
-#define UARTILPR 0x020\r
-#define UARTIBRD 0x024\r
-#define UARTFBRD 0x028\r
-#define UARTLCR_H 0x02C\r
-#define UARTCR 0x030\r
-#define UARTIFLS 0x034\r
-#define UARTIMSC 0x038\r
-#define UARTRIS 0x03C\r
-#define UARTMIS 0x040\r
-#define UARTICR 0x044\r
-#define UARTDMACR 0x048\r
-#endif\r
-\r
-#define UARTPID0 0xFE0\r
-#define UARTPID1 0xFE4\r
-#define UARTPID2 0xFE8\r
-#define UARTPID3 0xFEC\r
-\r
-// Data status bits\r
-#define UART_DATA_ERROR_MASK 0x0F00\r
-\r
-// Status reg bits\r
-#define UART_STATUS_ERROR_MASK 0x0F\r
-\r
-// Flag reg bits\r
-#if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE\r
-#define PL011_UARTFR_RI (1 << 0) // Ring indicator\r
-#define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty\r
-#define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full\r
-#define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full\r
-#define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty\r
-#define PL011_UARTFR_BUSY (1 << 8) // UART busy\r
-#define PL011_UARTFR_DCD (1 << 2) // Data carrier detect\r
-#define PL011_UARTFR_DSR (1 << 3) // Data set ready\r
-#define PL011_UARTFR_CTS (1 << 1) // Clear to send\r
-#else\r
-#define PL011_UARTFR_RI (1 << 8) // Ring indicator\r
-#define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty\r
-#define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full\r
-#define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full\r
-#define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty\r
-#define PL011_UARTFR_BUSY (1 << 3) // UART busy\r
-#define PL011_UARTFR_DCD (1 << 2) // Data carrier detect\r
-#define PL011_UARTFR_DSR (1 << 1) // Data set ready\r
-#define PL011_UARTFR_CTS (1 << 0) // Clear to send\r
-#endif\r
-\r
-// Flag reg bits - alternative names\r
-#define UART_TX_EMPTY_FLAG_MASK PL011_UARTFR_TXFE\r
-#define UART_RX_FULL_FLAG_MASK PL011_UARTFR_RXFF\r
-#define UART_TX_FULL_FLAG_MASK PL011_UARTFR_TXFF\r
-#define UART_RX_EMPTY_FLAG_MASK PL011_UARTFR_RXFE\r
-#define UART_BUSY_FLAG_MASK PL011_UARTFR_BUSY\r
-\r
-// Control reg bits\r
-#define PL011_UARTCR_CTSEN (1 << 15) // CTS hardware flow control enable\r
-#define PL011_UARTCR_RTSEN (1 << 14) // RTS hardware flow control enable\r
-#define PL011_UARTCR_RTS (1 << 11) // Request to send\r
-#define PL011_UARTCR_DTR (1 << 10) // Data transmit ready.\r
-#define PL011_UARTCR_RXE (1 << 9) // Receive enable\r
-#define PL011_UARTCR_TXE (1 << 8) // Transmit enable\r
-#define PL011_UARTCR_LBE (1 << 7) // Loopback enable\r
-#define PL011_UARTCR_UARTEN (1 << 0) // UART Enable\r
-\r
-// Line Control Register Bits\r
-#define PL011_UARTLCR_H_SPS (1 << 7) // Stick parity select\r
-#define PL011_UARTLCR_H_WLEN_8 (3 << 5)\r
-#define PL011_UARTLCR_H_WLEN_7 (2 << 5)\r
-#define PL011_UARTLCR_H_WLEN_6 (1 << 5)\r
-#define PL011_UARTLCR_H_WLEN_5 (0 << 5)\r
-#define PL011_UARTLCR_H_FEN (1 << 4) // FIFOs Enable\r
-#define PL011_UARTLCR_H_STP2 (1 << 3) // Two stop bits select\r
-#define PL011_UARTLCR_H_EPS (1 << 2) // Even parity select\r
-#define PL011_UARTLCR_H_PEN (1 << 1) // Parity Enable\r
-#define PL011_UARTLCR_H_BRK (1 << 0) // Send break\r
-\r
-#define PL011_UARTPID2_VER(X) (((X) >> 4) & 0xF)\r
-#define PL011_VER_R1P4 0x2\r
-\r
-/**\r
-\r
- Initialise the serial port to the specified settings.\r
- All unspecified settings will be set to the default values.\r
-\r
- @param[in] UartBase The base address of the serial device.\r
- @param[in] UartClkInHz The clock in Hz for the serial device.\r
- Ignored if the PCD PL011UartInteger is not 0\r
- @param[in out] BaudRate The baud rate of the serial device. If the\r
- baud rate is not supported, the speed will be\r
- reduced to the nearest supported one and the\r
- variable's value will be updated accordingly.\r
- @param[in out] ReceiveFifoDepth The number of characters the device will\r
- buffer on input. Value of 0 will use the\r
- device's default FIFO depth.\r
- @param[in out] Parity If applicable, this is the EFI_PARITY_TYPE\r
- that is computed or checked as each character\r
- is transmitted or received. If the device\r
- does not support parity, the value is the\r
- default parity value.\r
- @param[in out] DataBits The number of data bits in each character.\r
- @param[in out] StopBits If applicable, the EFI_STOP_BITS_TYPE number\r
- of stop bits per character.\r
- If the device does not support stop bits, the\r
- value is the default stop bit value.\r
-\r
- @retval RETURN_SUCCESS All attributes were set correctly on the\r
- serial device.\r
- @retval RETURN_INVALID_PARAMETER One or more of the attributes has an\r
- unsupported value.\r
-\r
-**/\r
-RETURN_STATUS\r
-EFIAPI\r
-PL011UartInitializePort (\r
- IN UINTN UartBase,\r
- IN UINT32 UartClkInHz,\r
- IN OUT UINT64 *BaudRate,\r
- IN OUT UINT32 *ReceiveFifoDepth,\r
- IN OUT EFI_PARITY_TYPE *Parity,\r
- IN OUT UINT8 *DataBits,\r
- IN OUT EFI_STOP_BITS_TYPE *StopBits\r
- );\r
-\r
-/**\r
-\r
- Assert or deassert the control signals on a serial port.\r
- The following control signals are set according their bit settings :\r
- . Request to Send\r
- . Data Terminal Ready\r
-\r
- @param[in] UartBase UART registers base address\r
- @param[in] Control The following bits are taken into account :\r
- . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the\r
- "Request To Send" control signal if this bit is\r
- equal to one/zero.\r
- . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert\r
- the "Data Terminal Ready" control signal if this\r
- bit is equal to one/zero.\r
- . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable\r
- the hardware loopback if this bit is equal to\r
- one/zero.\r
- . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.\r
- . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/\r
- disable the hardware flow control based on CTS (Clear\r
- To Send) and RTS (Ready To Send) control signals.\r
-\r
- @retval RETURN_SUCCESS The new control bits were set on the device.\r
- @retval RETURN_UNSUPPORTED The device does not support this operation.\r
-\r
-**/\r
-RETURN_STATUS\r
-EFIAPI\r
-PL011UartSetControl (\r
- IN UINTN UartBase,\r
- IN UINT32 Control\r
- );\r
-\r
-/**\r
-\r
- Retrieve the status of the control bits on a serial device.\r
-\r
- @param[in] UartBase UART registers base address\r
- @param[out] Control Status of the control bits on a serial device :\r
-\r
- . EFI_SERIAL_DATA_CLEAR_TO_SEND,\r
- EFI_SERIAL_DATA_SET_READY,\r
- EFI_SERIAL_RING_INDICATE,\r
- EFI_SERIAL_CARRIER_DETECT,\r
- EFI_SERIAL_REQUEST_TO_SEND,\r
- EFI_SERIAL_DATA_TERMINAL_READY\r
- are all related to the DTE (Data Terminal Equipment)\r
- and DCE (Data Communication Equipment) modes of\r
- operation of the serial device.\r
- . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the\r
- receive buffer is empty, 0 otherwise.\r
- . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the\r
- transmit buffer is empty, 0 otherwise.\r
- . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if\r
- the hardware loopback is enabled (the ouput feeds the\r
- receive buffer), 0 otherwise.\r
- . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if\r
- a loopback is accomplished by software, 0 otherwise.\r
- . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to\r
- one if the hardware flow control based on CTS (Clear\r
- To Send) and RTS (Ready To Send) control signals is\r
- enabled, 0 otherwise.\r
-\r
- @retval RETURN_SUCCESS The control bits were read from the serial device.\r
-\r
-**/\r
-RETURN_STATUS\r
-EFIAPI\r
-PL011UartGetControl (\r
- IN UINTN UartBase,\r
- OUT UINT32 *Control\r
- );\r
-\r
-/**\r
- Write data to serial device.\r
-\r
- @param Buffer Point of data buffer which need to be written.\r
- @param NumberOfBytes Number of output bytes which are cached in Buffer.\r
-\r
- @retval 0 Write data failed.\r
- @retval !0 Actual number of bytes written to serial device.\r
-\r
-**/\r
-UINTN\r
-EFIAPI\r
-PL011UartWrite (\r
- IN UINTN UartBase,\r
- IN UINT8 *Buffer,\r
- IN UINTN NumberOfBytes\r
- );\r
-\r
-/**\r
- Read data from serial device and save the data in buffer.\r
-\r
- @param Buffer Point of data buffer which need to be written.\r
- @param NumberOfBytes Number of output bytes which are cached in Buffer.\r
-\r
- @retval 0 Read data failed.\r
- @retval !0 Actual number of bytes read from serial device.\r
-\r
-**/\r
-UINTN\r
-EFIAPI\r
-PL011UartRead (\r
- IN UINTN UartBase,\r
- OUT UINT8 *Buffer,\r
- IN UINTN NumberOfBytes\r
- );\r
-\r
-/**\r
- Check to see if any data is available to be read from the debug device.\r
-\r
- @retval TRUE At least one byte of data is available to be read\r
- @retval FALSE No data is available to be read\r
-\r
-**/\r
-BOOLEAN\r
-EFIAPI\r
-PL011UartPoll (\r
- IN UINTN UartBase\r
- );\r
-\r
-#endif\r
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