ArmPlatformPkg: PL061 - rewrite the hardware interaction

[mirror_edk2.git] / ArmPlatformPkg / Include / Drivers / PL031RealTimeClock.h

diff --git a/ArmPlatformPkg/Include/Drivers/PL031RealTimeClock.h b/ArmPlatformPkg/Include/Drivers/PL031RealTimeClock.h
index 8c26d6605348d0879581ab0d7d5949137887af32..76fbd0eb8225f68f3867a42a36adfcf9f52c85c1 100644 (file)
--- a/ArmPlatformPkg/Include/Drivers/PL031RealTimeClock.h
+++ b/ArmPlatformPkg/Include/Drivers/PL031RealTimeClock.h
@@ -1,6 +1,6 @@
 /** @file\r
 *\r
-*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+*  Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
 *\r
 *  This program and the accompanying materials\r
 *  are licensed and made available under the terms and conditions of the BSD License\r
@@ -16,26 +16,23 @@
 #ifndef __PL031_REAL_TIME_CLOCK_H__\r
 #define __PL031_REAL_TIME_CLOCK_H__\r
 \r
-#include <Base.h>\r
-#include <ArmPlatform.h>\r
-\r
 // PL031 Registers\r
-#define PL031_RTC_DR_DATA_REGISTER                      (PL031_RTC_BASE + 0x000)\r
-#define PL031_RTC_MR_MATCH_REGISTER                     (PL031_RTC_BASE + 0x004)\r
-#define PL031_RTC_LR_LOAD_REGISTER                      (PL031_RTC_BASE + 0x008)\r
-#define PL031_RTC_CR_CONTROL_REGISTER                   (PL031_RTC_BASE + 0x00C)\r
-#define PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER      (PL031_RTC_BASE + 0x010)\r
-#define PL031_RTC_RIS_RAW_IRQ_STATUS_REGISTER           (PL031_RTC_BASE + 0x014)\r
-#define PL031_RTC_MIS_MASKED_IRQ_STATUS_REGISTER        (PL031_RTC_BASE + 0x018)\r
-#define PL031_RTC_ICR_IRQ_CLEAR_REGISTER                (PL031_RTC_BASE + 0x01C)\r
-#define PL031_RTC_PERIPH_ID0                            (PL031_RTC_BASE + 0xFE0)\r
-#define PL031_RTC_PERIPH_ID1                            (PL031_RTC_BASE + 0xFE4)\r
-#define PL031_RTC_PERIPH_ID2                            (PL031_RTC_BASE + 0xFE8)\r
-#define PL031_RTC_PERIPH_ID3                            (PL031_RTC_BASE + 0xFEC)\r
-#define PL031_RTC_PCELL_ID0                             (PL031_RTC_BASE + 0xFF0)\r
-#define PL031_RTC_PCELL_ID1                             (PL031_RTC_BASE + 0xFF4)\r
-#define PL031_RTC_PCELL_ID2                             (PL031_RTC_BASE + 0xFF8)\r
-#define PL031_RTC_PCELL_ID3                             (PL031_RTC_BASE + 0xFFC)\r
+#define PL031_RTC_DR_DATA_REGISTER                      0x000\r
+#define PL031_RTC_MR_MATCH_REGISTER                     0x004\r
+#define PL031_RTC_LR_LOAD_REGISTER                      0x008\r
+#define PL031_RTC_CR_CONTROL_REGISTER                   0x00C\r
+#define PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER      0x010\r
+#define PL031_RTC_RIS_RAW_IRQ_STATUS_REGISTER           0x014\r
+#define PL031_RTC_MIS_MASKED_IRQ_STATUS_REGISTER        0x018\r
+#define PL031_RTC_ICR_IRQ_CLEAR_REGISTER                0x01C\r
+#define PL031_RTC_PERIPH_ID0                            0xFE0\r
+#define PL031_RTC_PERIPH_ID1                            0xFE4\r
+#define PL031_RTC_PERIPH_ID2                            0xFE8\r
+#define PL031_RTC_PERIPH_ID3                            0xFEC\r
+#define PL031_RTC_PCELL_ID0                             0xFF0\r
+#define PL031_RTC_PCELL_ID1                             0xFF4\r
+#define PL031_RTC_PCELL_ID2                             0xFF8\r
+#define PL031_RTC_PCELL_ID3                             0xFFC\r
 \r
 // PL031 Values\r
 #define PL031_RTC_ENABLED                               0x00000001\r