ArmPlatformPkg: Add PL061 GPIO driver

[mirror_edk2.git] / ArmPlatformPkg / Include / Drivers / PL061Gpio.h

diff --git a/ArmPlatformPkg/Include/Drivers/PL061Gpio.h b/ArmPlatformPkg/Include/Drivers/PL061Gpio.h
new file mode 100644 (file)
index 0000000..4daabff
--- /dev/null
+++ b/ArmPlatformPkg/Include/Drivers/PL061Gpio.h
@@ -0,0 +1,56 @@
+/** @file\r
+*\r
+*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+*\r
+*  This program and the accompanying materials\r
+*  are licensed and made available under the terms and conditions of the BSD License\r
+*  which accompanies this distribution.  The full text of the license may be found at\r
+*  http://opensource.org/licenses/bsd-license.php\r
+*\r
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+\r
+#ifndef __PL061_GPIO_H__\r
+#define __PL061_GPIO_H__\r
+\r
+#include <Base.h>\r
+#include <Protocol/EmbeddedGpio.h>\r
+#include <ArmPlatform.h>\r
+\r
+// SP805 Watchdog Registers\r
+#define PL061_GPIO_DATA_REG             (PL061_GPIO_BASE + 0x000)\r
+#define PL061_GPIO_DIR_REG              (PL061_GPIO_BASE + 0x400)\r
+#define PL061_GPIO_IS_REG               (PL061_GPIO_BASE + 0x404)\r
+#define PL061_GPIO_IBE_REG              (PL061_GPIO_BASE + 0x408)\r
+#define PL061_GPIO_IEV_REG              (PL061_GPIO_BASE + 0x40C)\r
+#define PL061_GPIO_IE_REG               (PL061_GPIO_BASE + 0x410)\r
+#define PL061_GPIO_RIS_REG              (PL061_GPIO_BASE + 0x414)\r
+#define PL061_GPIO_MIS_REG              (PL061_GPIO_BASE + 0x410)\r
+#define PL061_GPIO_IC_REG               (PL061_GPIO_BASE + 0x41C)\r
+#define PL061_GPIO_AFSEL_REG            (PL061_GPIO_BASE + 0x420)\r
+\r
+#define PL061_GPIO_PERIPH_ID0           (PL061_GPIO_BASE + 0xFE0)\r
+#define PL061_GPIO_PERIPH_ID1           (PL061_GPIO_BASE + 0xFE4)\r
+#define PL061_GPIO_PERIPH_ID2           (PL061_GPIO_BASE + 0xFE8)\r
+#define PL061_GPIO_PERIPH_ID3           (PL061_GPIO_BASE + 0xFEC)\r
+\r
+#define PL061_GPIO_PCELL_ID0            (PL061_GPIO_BASE + 0xFF0)\r
+#define PL061_GPIO_PCELL_ID1            (PL061_GPIO_BASE + 0xFF4)\r
+#define PL061_GPIO_PCELL_ID2            (PL061_GPIO_BASE + 0xFF8)\r
+#define PL061_GPIO_PCELL_ID3            (PL061_GPIO_BASE + 0xFFC)\r
+\r
+\r
+// GPIO pins are numbered 0..7\r
+#define LAST_GPIO_PIN                   7\r
+\r
+// All bits low except one bit high, native bit lenght\r
+#define GPIO_PIN_MASK(Pin)              (1UL << ((UINTN)(Pin)))\r
+// All bits low except one bit high, restricted to 8 bits (i.e. ensures zeros above 8bits)\r
+#define GPIO_PIN_MASK_HIGH_8BIT(Pin)    (GPIO_PIN_MASK(Pin) && 0xFF)\r
+// All bits high except one bit low, restricted to 8 bits (i.e. ensures zeros above 8bits)\r
+#define GPIO_PIN_MASK_LOW_8BIT(Pin)     ((~GPIO_PIN_MASK(Pin)) && 0xFF)\r
+\r
+#endif  // __PL061_GPIO_H__\r