ArmPlatformPkg: Minor code changes (comments, misspellings, coding stylei, line endings)

[mirror_edk2.git] / ArmPlatformPkg / Include / Drivers / PL061Gpio.h

diff --git a/ArmPlatformPkg/Include/Drivers/PL061Gpio.h b/ArmPlatformPkg/Include/Drivers/PL061Gpio.h
index 4daabff768a874c3bcf9980c49fbd22398725e0f..38458f484476360f2ad31644f493e53f342d9289 100644 (file)
--- a/ArmPlatformPkg/Include/Drivers/PL061Gpio.h
+++ b/ArmPlatformPkg/Include/Drivers/PL061Gpio.h
@@ -1,6 +1,6 @@
 /** @file\r
 *\r
-*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
 *\r
 *  This program and the accompanying materials\r
 *  are licensed and made available under the terms and conditions of the BSD License\r
@@ -16,37 +16,35 @@
 #ifndef __PL061_GPIO_H__\r
 #define __PL061_GPIO_H__\r
 \r
-#include <Base.h>\r
 #include <Protocol/EmbeddedGpio.h>\r
-#include <ArmPlatform.h>\r
-\r
-// SP805 Watchdog Registers\r
-#define PL061_GPIO_DATA_REG             (PL061_GPIO_BASE + 0x000)\r
-#define PL061_GPIO_DIR_REG              (PL061_GPIO_BASE + 0x400)\r
-#define PL061_GPIO_IS_REG               (PL061_GPIO_BASE + 0x404)\r
-#define PL061_GPIO_IBE_REG              (PL061_GPIO_BASE + 0x408)\r
-#define PL061_GPIO_IEV_REG              (PL061_GPIO_BASE + 0x40C)\r
-#define PL061_GPIO_IE_REG               (PL061_GPIO_BASE + 0x410)\r
-#define PL061_GPIO_RIS_REG              (PL061_GPIO_BASE + 0x414)\r
-#define PL061_GPIO_MIS_REG              (PL061_GPIO_BASE + 0x410)\r
-#define PL061_GPIO_IC_REG               (PL061_GPIO_BASE + 0x41C)\r
-#define PL061_GPIO_AFSEL_REG            (PL061_GPIO_BASE + 0x420)\r
-\r
-#define PL061_GPIO_PERIPH_ID0           (PL061_GPIO_BASE + 0xFE0)\r
-#define PL061_GPIO_PERIPH_ID1           (PL061_GPIO_BASE + 0xFE4)\r
-#define PL061_GPIO_PERIPH_ID2           (PL061_GPIO_BASE + 0xFE8)\r
-#define PL061_GPIO_PERIPH_ID3           (PL061_GPIO_BASE + 0xFEC)\r
-\r
-#define PL061_GPIO_PCELL_ID0            (PL061_GPIO_BASE + 0xFF0)\r
-#define PL061_GPIO_PCELL_ID1            (PL061_GPIO_BASE + 0xFF4)\r
-#define PL061_GPIO_PCELL_ID2            (PL061_GPIO_BASE + 0xFF8)\r
-#define PL061_GPIO_PCELL_ID3            (PL061_GPIO_BASE + 0xFFC)\r
+\r
+// PL061 GPIO Registers\r
+#define PL061_GPIO_DATA_REG             ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x000)\r
+#define PL061_GPIO_DIR_REG              ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x400)\r
+#define PL061_GPIO_IS_REG               ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x404)\r
+#define PL061_GPIO_IBE_REG              ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x408)\r
+#define PL061_GPIO_IEV_REG              ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x40C)\r
+#define PL061_GPIO_IE_REG               ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x410)\r
+#define PL061_GPIO_RIS_REG              ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x414)\r
+#define PL061_GPIO_MIS_REG              ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x410)\r
+#define PL061_GPIO_IC_REG               ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x41C)\r
+#define PL061_GPIO_AFSEL_REG            ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x420)\r
+\r
+#define PL061_GPIO_PERIPH_ID0           ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFE0)\r
+#define PL061_GPIO_PERIPH_ID1           ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFE4)\r
+#define PL061_GPIO_PERIPH_ID2           ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFE8)\r
+#define PL061_GPIO_PERIPH_ID3           ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFEC)\r
+\r
+#define PL061_GPIO_PCELL_ID0            ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFF0)\r
+#define PL061_GPIO_PCELL_ID1            ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFF4)\r
+#define PL061_GPIO_PCELL_ID2            ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFF8)\r
+#define PL061_GPIO_PCELL_ID3            ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFFC)\r
 \r
 \r
 // GPIO pins are numbered 0..7\r
 #define LAST_GPIO_PIN                   7\r
 \r
-// All bits low except one bit high, native bit lenght\r
+// All bits low except one bit high, native bit length\r
 #define GPIO_PIN_MASK(Pin)              (1UL << ((UINTN)(Pin)))\r
 // All bits low except one bit high, restricted to 8 bits (i.e. ensures zeros above 8bits)\r
 #define GPIO_PIN_MASK_HIGH_8BIT(Pin)    (GPIO_PIN_MASK(Pin) && 0xFF)\r