\r
\r
typedef struct {\r
- UINTN HasQos; // has QoS registers\r
- UINTN MaxChip; // number of memory chips accessible\r
- BOOLEAN IsUserCfg;\r
+ UINTN HasQos; // has QoS registers\r
+ UINTN MaxChip; // number of memory chips accessible\r
+ BOOLEAN IsUserCfg;\r
UINT32 User0Cfg;\r
UINT32 User2Cfg;\r
- UINT32 RefreshPeriod;\r
- UINT32 CasLatency;\r
- UINT32 WriteLatency;\r
- UINT32 t_mrd;\r
- UINT32 t_ras;\r
- UINT32 t_rc;\r
- UINT32 t_rcd;\r
- UINT32 t_rfc;\r
- UINT32 t_rp;\r
- UINT32 t_rrd;\r
- UINT32 t_wr;\r
- UINT32 t_wtr;\r
- UINT32 t_xp;\r
- UINT32 t_xsr;\r
- UINT32 t_esr;\r
- UINT32 MemoryCfg;\r
- UINT32 MemoryCfg2;\r
- UINT32 MemoryCfg3;\r
- UINT32 ChipCfg0;\r
- UINT32 ChipCfg1;\r
- UINT32 ChipCfg2;\r
- UINT32 ChipCfg3;\r
- UINT32 t_faw;\r
- UINT32 t_data_en;\r
- UINT32 t_wdata_en;\r
+ UINT32 RefreshPeriod;\r
+ UINT32 CasLatency;\r
+ UINT32 WriteLatency;\r
+ UINT32 t_mrd;\r
+ UINT32 t_ras;\r
+ UINT32 t_rc;\r
+ UINT32 t_rcd;\r
+ UINT32 t_rfc;\r
+ UINT32 t_rp;\r
+ UINT32 t_rrd;\r
+ UINT32 t_wr;\r
+ UINT32 t_wtr;\r
+ UINT32 t_xp;\r
+ UINT32 t_xsr;\r
+ UINT32 t_esr;\r
+ UINT32 MemoryCfg;\r
+ UINT32 MemoryCfg2;\r
+ UINT32 MemoryCfg3;\r
+ UINT32 ChipCfg0;\r
+ UINT32 ChipCfg1;\r
+ UINT32 ChipCfg2;\r
+ UINT32 ChipCfg3;\r
+ UINT32 t_faw;\r
+ UINT32 t_data_en;\r
+ UINT32 t_wdata_en;\r
UINT32 ModeReg;\r
UINT32 ExtModeReg;\r
} PL341_DMC_CONFIG;\r
#define DMC_MEMORY_CFG2_REG 0x4C\r
#define DMC_MEMORY_CFG3_REG 0x50\r
#define DMC_T_FAW_REG 0x54\r
-#define DMC_T_RDATA_EN 0x5C /* DFI read data enable register */\r
+#define DMC_T_RDATA_EN 0x5C /* DFI read data enable register */\r
#define DMC_T_WRLAT_DIFF 0x60 /* DFI write data enable register */\r
\r
// Returns the state of the memory controller:\r
//\r
// PHY Register Settings\r
//\r
-#define PHY_PTM_DFI_CLK_RANGE 0xE00 // DDR2 PHY PTM register offset\r
-#define PHY_PTM_IOTERM 0xE04\r
-#define PHY_PTM_PLL_EN 0xe0c\r
-#define PHY_PTM_PLL_RANGE 0xe18\r
-#define PHY_PTM_FEEBACK_DIV 0xe1c\r
-#define PHY_PTM_RCLK_DIV 0xe20\r
-#define PHY_PTM_LOCK_STATUS 0xe28\r
-#define PHY_PTM_INIT_DONE 0xe34\r
-#define PHY_PTM_ADDCOM_IOSTR_OFF 0xec8\r
-#define PHY_PTM_SQU_TRAINING 0xee8\r
-#define PHY_PTM_SQU_STAT 0xeec\r
+#define PHY_PTM_DFI_CLK_RANGE 0xE00 // DDR2 PHY PTM register offset\r
+#define PHY_PTM_IOTERM 0xE04\r
+#define PHY_PTM_PLL_EN 0xe0c\r
+#define PHY_PTM_PLL_RANGE 0xe18\r
+#define PHY_PTM_FEEBACK_DIV 0xe1c\r
+#define PHY_PTM_RCLK_DIV 0xe20\r
+#define PHY_PTM_LOCK_STATUS 0xe28\r
+#define PHY_PTM_INIT_DONE 0xe34\r
+#define PHY_PTM_ADDCOM_IOSTR_OFF 0xec8\r
+#define PHY_PTM_SQU_TRAINING 0xee8\r
+#define PHY_PTM_SQU_STAT 0xeec\r
\r
// ==============================================================================\r
// PIPD 40G DDR2/DDR3 PHY Register definitions\r
//\r
// Offsets from APB Base Address\r
// ==============================================================================\r
-#define PHY_BYTE0_OFFSET 0x000\r
-#define PHY_BYTE1_OFFSET 0x200\r
-#define PHY_BYTE2_OFFSET 0x400\r
-#define PHY_BYTE3_OFFSET 0x600\r
+#define PHY_BYTE0_OFFSET 0x000\r
+#define PHY_BYTE1_OFFSET 0x200\r
+#define PHY_BYTE2_OFFSET 0x400\r
+#define PHY_BYTE3_OFFSET 0x600\r
\r
-#define PHY_BYTE0_COARSE_SQADJ_INIT 0x064 ;// Coarse squelch adjust\r
-#define PHY_BYTE1_COARSE_SQADJ_INIT 0x264 ;// Coarse squelch adjust\r
-#define PHY_BYTE2_COARSE_SQADJ_INIT 0x464 ;// Coarse squelch adjust\r
-#define PHY_BYTE3_COARSE_SQADJ_INIT 0x664 ;// Coarse squelch adjust\r
+#define PHY_BYTE0_COARSE_SQADJ_INIT 0x064 ;// Coarse squelch adjust\r
+#define PHY_BYTE1_COARSE_SQADJ_INIT 0x264 ;// Coarse squelch adjust\r
+#define PHY_BYTE2_COARSE_SQADJ_INIT 0x464 ;// Coarse squelch adjust\r
+#define PHY_BYTE3_COARSE_SQADJ_INIT 0x664 ;// Coarse squelch adjust\r
\r
-#define PHY_BYTE0_IOSTR_OFFSET 0x004\r
-#define PHY_BYTE1_IOSTR_OFFSET 0x204\r
-#define PHY_BYTE2_IOSTR_OFFSET 0x404\r
-#define PHY_BYTE3_IOSTR_OFFSET 0x604\r
+#define PHY_BYTE0_IOSTR_OFFSET 0x004\r
+#define PHY_BYTE1_IOSTR_OFFSET 0x204\r
+#define PHY_BYTE2_IOSTR_OFFSET 0x404\r
+#define PHY_BYTE3_IOSTR_OFFSET 0x604\r
\r
\r
;//--------------------------------------------------------------------------\r
\r
// DFI Clock ranges:\r
\r
-#define PHY_PTM_DFI_CLK_RANGE_200MHz 0x0\r
-#define PHY_PTM_DFI_CLK_RANGE_201_267MHz 0x1\r
-#define PHY_PTM_DFI_CLK_RANGE_268_333MHz 0x2\r
-#define PHY_PTM_DFI_CLK_RANGE_334_400MHz 0x3\r
-#define PHY_PTM_DFI_CLK_RANGE_401_533MHz 0x4\r
-#define PHY_PTM_DFI_CLK_RANGE_534_667MHz 0x5\r
-#define PHY_PTM_DFI_CLK_RANGE_668_800MHz 0x6\r
+#define PHY_PTM_DFI_CLK_RANGE_200MHz 0x0\r
+#define PHY_PTM_DFI_CLK_RANGE_201_267MHz 0x1\r
+#define PHY_PTM_DFI_CLK_RANGE_268_333MHz 0x2\r
+#define PHY_PTM_DFI_CLK_RANGE_334_400MHz 0x3\r
+#define PHY_PTM_DFI_CLK_RANGE_401_533MHz 0x4\r
+#define PHY_PTM_DFI_CLK_RANGE_534_667MHz 0x5\r
+#define PHY_PTM_DFI_CLK_RANGE_668_800MHz 0x6\r
\r
\r
\r
-#define PHY_PTM_DFI_CLK_RANGE_VAL PHY_PTM_DFI_CLK_RANGE_334_400MHz\r
+#define PHY_PTM_DFI_CLK_RANGE_VAL PHY_PTM_DFI_CLK_RANGE_334_400MHz\r
\r
//--------------------------------------------------------------------------\r
\r
\r
// PLL Range\r
\r
-#define PHY_PTM_PLL_RANGE_200_400MHz 0x0 // b0 = frequency >= 200 MHz and < 400 MHz\r
-#define PHY_PTM_PLL_RANGE_400_800MHz 0x1 // b1 = frequency >= 400 MHz.\r
-#define PHY_PTM_FEEBACK_DIV_200_400MHz 0x0 // b0 = frequency >= 200 MHz and < 400 MHz\r
-#define PHY_PTM_FEEBACK_DIV_400_800MHz 0x1 // b1 = frequency >= 400 MHz.\r
-#define PHY_PTM_REFCLK_DIV_200_400MHz 0x0\r
-#define PHY_PTM_REFCLK_DIV_400_800MHz 0x1\r
+#define PHY_PTM_PLL_RANGE_200_400MHz 0x0 // b0 = frequency >= 200 MHz and < 400 MHz\r
+#define PHY_PTM_PLL_RANGE_400_800MHz 0x1 // b1 = frequency >= 400 MHz.\r
+#define PHY_PTM_FEEBACK_DIV_200_400MHz 0x0 // b0 = frequency >= 200 MHz and < 400 MHz\r
+#define PHY_PTM_FEEBACK_DIV_400_800MHz 0x1 // b1 = frequency >= 400 MHz.\r
+#define PHY_PTM_REFCLK_DIV_200_400MHz 0x0\r
+#define PHY_PTM_REFCLK_DIV_400_800MHz 0x1\r
\r
#define TC_UIOLHNC_MASK 0x000003C0\r
#define TC_UIOLHNC_SHIFT 0x6\r
#define TC_UIOHSTOP_SHIFT 0x0\r
#define TC_UIOLHXC_VALUE 0x4\r
\r
-#define PHY_PTM_SQU_TRAINING_ENABLE 0x1\r
-#define PHY_PTM_SQU_TRAINING_DISABLE 0x0\r
+#define PHY_PTM_SQU_TRAINING_ENABLE 0x1\r
+#define PHY_PTM_SQU_TRAINING_DISABLE 0x0\r
\r
\r
//--------------------------------------\r
// JEDEC DDR2 Device Register definitions and settings\r
//--------------------------------------\r
-#define DDR_MODESET_SHFT 14\r
-#define DDR_MODESET_MR 0x0 ;// Mode register\r
-#define DDR_MODESET_EMR 0x1 ;// Extended Mode register\r
-#define DDR_MODESET_EMR2 0x2\r
-#define DDR_MODESET_EMR3 0x3\r
+#define DDR_MODESET_SHFT 14\r
+#define DDR_MODESET_MR 0x0 ;// Mode register\r
+#define DDR_MODESET_EMR 0x1 ;// Extended Mode register\r
+#define DDR_MODESET_EMR2 0x2\r
+#define DDR_MODESET_EMR3 0x3\r
\r
//\r
// Extended Mode Register settings\r
\r
#define DDR_EMR_ODS_VAL DDR_EMR_ODS_FULL\r
\r
-#define DDR_SDRAM_START_ADDR 0x10000000\r
+#define DDR_SDRAM_START_ADDR 0x10000000\r
\r
\r
// ----------------------------------------\r
// PHY IOTERM values\r
// ----------------------------------------\r
-#define PHY_PTM_IOTERM_OFF 0x0\r
-#define PHY_PTM_IOTERM_150R 0x1\r
-#define PHY_PTM_IOTERM_75R 0x2\r
-#define PHY_PTM_IOTERM_50R 0x3\r
-\r
-#define PHY_BYTE_IOSTR_60OHM 0x0\r
-#define PHY_BYTE_IOSTR_40OHM 0x1\r
-#define PHY_BYTE_IOSTR_30OHM 0x2\r
-#define PHY_BYTE_IOSTR_30AOHM 0x3\r
+#define PHY_PTM_IOTERM_OFF 0x0\r
+#define PHY_PTM_IOTERM_150R 0x1\r
+#define PHY_PTM_IOTERM_75R 0x2\r
+#define PHY_PTM_IOTERM_50R 0x3\r
+\r
+#define PHY_BYTE_IOSTR_60OHM 0x0\r
+#define PHY_BYTE_IOSTR_40OHM 0x1\r
+#define PHY_BYTE_IOSTR_30OHM 0x2\r
+#define PHY_BYTE_IOSTR_30AOHM 0x3\r
\r
#define DDR2_MR_BURST_LENGTH_4 (2)\r
#define DDR2_MR_BURST_LENGTH_8 (3)\r
projects / mirror_edk2.git / blobdiff