Check the input VaraibleName for db/dbx when appending variables with formatted as...

[mirror_edk2.git] / ArmPlatformPkg / Include / Drivers / PL35xSmc.h

diff --git a/ArmPlatformPkg/Include/Drivers/PL35xSmc.h b/ArmPlatformPkg/Include/Drivers/PL35xSmc.h
index 0da47f99827bd9ab9cd9e47ac9270e5c3e008ae2..750f5088b6de5a3f6ffe191e109f9d8461a8eb28 100644 (file)
--- a/ArmPlatformPkg/Include/Drivers/PL35xSmc.h
+++ b/ArmPlatformPkg/Include/Drivers/PL35xSmc.h
@@ -1,6 +1,6 @@
 /** @file\r
 *\r
-*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
 *\r
 *  This program and the accompanying materials\r
 *  are licensed and made available under the terms and conditions of the BSD License\r
@@ -12,46 +12,64 @@
 *\r
 **/\r
 \r
-#ifndef PL354SMC_H_\r
-#define PL354SMC_H_\r
+#ifndef PL35xSMC_H_\r
+#define PL35xSMC_H_\r
 \r
-#define PL354_SMC_DIRECT_CMD_OFFSET  0x10\r
-#define PL354_SMC_SET_CYCLES_OFFSET  0x14\r
-#define PL354_SMC_SET_OPMODE_OFFSET  0x18\r
+#define PL350_SMC_DIRECT_CMD_OFFSET   0x10\r
+#define PL350_SMC_SET_CYCLES_OFFSET   0x14\r
+#define PL350_SMC_SET_OPMODE_OFFSET   0x18\r
+#define PL350_SMC_REFRESH_0_OFFSET    0x20\r
+#define PL350_SMC_REFRESH_1_OFFSET    0x24\r
 \r
-#define PL354_SMC_DIRECT_CMD_ADDR(addr)             ((addr) & 0xFFFFF)\r
-#define PL354_SMC_DIRECT_CMD_ADDR_SET_CRE           (1 << 20)\r
-#define PL354_SMC_DIRECT_CMD_ADDR_CMD_MODE_UPDATE   (3 << 21)\r
-#define PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE        (2 << 21)\r
-#define PL354_SMC_DIRECT_CMD_ADDR_CMD_MODE          (1 << 21)\r
-#define PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE_AXI    (0 << 21)\r
-#define PL354_SMC_DIRECT_CMD_ADDR_CS(interf,chip)   (((interf) << 25) | ((chip) << 23))\r
+#define PL350_SMC_DIRECT_CMD_ADDR(addr)                 ((addr) & 0xFFFFF)\r
+#define PL350_SMC_DIRECT_CMD_ADDR_SET_CRE               (1 << 20)\r
+#define PL350_SMC_DIRECT_CMD_ADDR_CMD_MODE_UPDATE       (3 << 21)\r
+#define PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE            (2 << 21)\r
+#define PL350_SMC_DIRECT_CMD_ADDR_CMD_MODE              (1 << 21)\r
+#define PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE_AXI        (0 << 21)\r
+#define PL350_SMC_DIRECT_CMD_ADDR_CS_INTERF(interf,chip) (((interf) << 25) | ((chip) << 23))\r
+#define PL350_SMC_DIRECT_CMD_ADDR_CS(ChipSelect)        (((ChipSelect) & 0x7) << 23)\r
 \r
-#define PL354_SMC_SET_OPMODE_MEM_WIDTH_8                (0 << 0)\r
-#define PL354_SMC_SET_OPMODE_MEM_WIDTH_16               (1 << 0)\r
-#define PL354_SMC_SET_OPMODE_MEM_WIDTH_32               (2 << 0)\r
-#define PL354_SMC_SET_OPMODE_SET_RD_SYNC                (1 << 2)\r
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_1      (0 << 3)\r
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_4      (1 << 3)\r
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_8      (2 << 3)\r
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_16     (3 << 3)\r
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_32     (4 << 3)\r
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT   (5 << 3)\r
-#define PL354_SMC_SET_OPMODE_SET_WR_SYNC                (1 << 6)\r
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_1      (0 << 7)\r
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_4      (1 << 7)\r
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_8      (2 << 7)\r
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_16     (3 << 7)\r
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_32     (4 << 7)\r
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT   (5 << 7)\r
-#define PL354_SMC_SET_OPMODE_SET_BAA                    (1 << 10)\r
-#define PL354_SMC_SET_OPMODE_SET_ADV                    (1 << 11)\r
-#define PL354_SMC_SET_OPMODE_SET_BLS                    (1 << 12)\r
-#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_ANY        (0 << 13)\r
-#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_32         (1 << 13)\r
-#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_64         (2 << 13)\r
-#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_128        (3 << 13)\r
-#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_256        (4 << 13)\r
+#define PL350_SMC_SET_OPMODE_MEM_WIDTH_8                (0 << 0)\r
+#define PL350_SMC_SET_OPMODE_MEM_WIDTH_16               (1 << 0)\r
+#define PL350_SMC_SET_OPMODE_MEM_WIDTH_32               (2 << 0)\r
+#define PL350_SMC_SET_OPMODE_SET_RD_SYNC                (1 << 2)\r
+#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_1      (0 << 3)\r
+#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_4      (1 << 3)\r
+#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_8      (2 << 3)\r
+#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_16     (3 << 3)\r
+#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_32     (4 << 3)\r
+#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT   (5 << 3)\r
+#define PL350_SMC_SET_OPMODE_SET_WR_SYNC                (1 << 6)\r
+#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_1      (0 << 7)\r
+#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_4      (1 << 7)\r
+#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_8      (2 << 7)\r
+#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_16     (3 << 7)\r
+#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_32     (4 << 7)\r
+#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT   (5 << 7)\r
+#define PL350_SMC_SET_OPMODE_SET_BAA                    (1 << 10)\r
+#define PL350_SMC_SET_OPMODE_SET_ADV                    (1 << 11)\r
+#define PL350_SMC_SET_OPMODE_SET_BLS                    (1 << 12)\r
+#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_ANY        (0 << 13)\r
+#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_32         (1 << 13)\r
+#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_64         (2 << 13)\r
+#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_128        (3 << 13)\r
+#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_256        (4 << 13)\r
 \r
+#define PL350_SMC_SET_CYCLE_NAND_T_RC(t)                (((t) & 0xF) << 0)\r
+#define PL350_SMC_SET_CYCLE_NAND_T_WC(t)                (((t) & 0xF) << 4)\r
+#define PL350_SMC_SET_CYCLE_NAND_T_REA(t)              (((t) & 0x7) << 8)\r
+#define PL350_SMC_SET_CYCLE_NAND_T_WP(t)                (((t) & 0x7) << 11)\r
+#define PL350_SMC_SET_CYCLE_NAND_T_CLR(t)                (((t) & 0x7) << 14)\r
+#define PL350_SMC_SET_CYCLE_NAND_T_AR(t)                (((t) & 0x7) << 17)\r
+#define PL350_SMC_SET_CYCLE_NAND_T_RR(t)                (((t) & 0x7) << 20)\r
+\r
+#define PL350_SMC_SET_CYCLE_SRAM_T_RC(t)                (((t) & 0xF) << 0)\r
+#define PL350_SMC_SET_CYCLE_SRAM_T_WC(t)                (((t) & 0xF) << 4)\r
+#define PL350_SMC_SET_CYCLE_SRAM_T_CEOE(t)              (((t) & 0x7) << 8)\r
+#define PL350_SMC_SET_CYCLE_SRAM_T_WP(t)                (((t) & 0x7) << 11)\r
+#define PL350_SMC_SET_CYCLE_SRAM_T_PC(t)                (((t) & 0x7) << 14)\r
+#define PL350_SMC_SET_CYCLE_SRAM_T_TR(t)                (((t) & 0x7) << 17)\r
+#define PL350_SMC_SET_CYCLE_SRAM_WE_TIME                (1 << 20)\r
 \r
 #endif\r