// EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE is the only\r
// control bit that is not supported.\r
//\r
-STATIC CONST UINT32 mInvalidControlBits = EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE;\r
+STATIC CONST UINT32 mInvalidControlBits = EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE;\r
\r
/**\r
\r
IN OUT EFI_STOP_BITS_TYPE *StopBits\r
)\r
{\r
- UINT32 LineControl;\r
- UINT32 Divisor;\r
- UINT32 Integer;\r
- UINT32 Fractional;\r
- UINT32 HardwareFifoDepth;\r
- UINT32 UartPid2;\r
+ UINT32 LineControl;\r
+ UINT32 Divisor;\r
+ UINT32 Integer;\r
+ UINT32 Fractional;\r
+ UINT32 HardwareFifoDepth;\r
+ UINT32 UartPid2;\r
\r
HardwareFifoDepth = FixedPcdGet16 (PcdUartDefaultReceiveFifoDepth);\r
if (HardwareFifoDepth == 0) {\r
- UartPid2 = MmioRead32 (UartBase + UARTPID2);\r
+ UartPid2 = MmioRead32 (UartBase + UARTPID2);\r
HardwareFifoDepth = (PL011_UARTPID2_VER (UartPid2) > PL011_VER_R1P4) ? 32 : 16;\r
}\r
\r
// down, there is no maximum FIFO size.\r
if ((*ReceiveFifoDepth == 0) || (*ReceiveFifoDepth >= HardwareFifoDepth)) {\r
// Enable FIFO\r
- LineControl = PL011_UARTLCR_H_FEN;\r
+ LineControl = PL011_UARTLCR_H_FEN;\r
*ReceiveFifoDepth = HardwareFifoDepth;\r
} else {\r
// Disable FIFO\r
// Parity\r
//\r
switch (*Parity) {\r
- case DefaultParity:\r
- *Parity = NoParity;\r
- case NoParity:\r
- // Nothing to do. Parity is disabled by default.\r
- break;\r
- case EvenParity:\r
- LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_EPS);\r
- break;\r
- case OddParity:\r
- LineControl |= PL011_UARTLCR_H_PEN;\r
- break;\r
- case MarkParity:\r
- LineControl |= ( PL011_UARTLCR_H_PEN \\r
- | PL011_UARTLCR_H_SPS \\r
- | PL011_UARTLCR_H_EPS);\r
- break;\r
- case SpaceParity:\r
- LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_SPS);\r
- break;\r
- default:\r
- return RETURN_INVALID_PARAMETER;\r
+ case DefaultParity:\r
+ *Parity = NoParity;\r
+ case NoParity:\r
+ // Nothing to do. Parity is disabled by default.\r
+ break;\r
+ case EvenParity:\r
+ LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_EPS);\r
+ break;\r
+ case OddParity:\r
+ LineControl |= PL011_UARTLCR_H_PEN;\r
+ break;\r
+ case MarkParity:\r
+ LineControl |= (PL011_UARTLCR_H_PEN \\r
+ | PL011_UARTLCR_H_SPS \\r
+ | PL011_UARTLCR_H_EPS);\r
+ break;\r
+ case SpaceParity:\r
+ LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_SPS);\r
+ break;\r
+ default:\r
+ return RETURN_INVALID_PARAMETER;\r
}\r
\r
//\r
// Data Bits\r
//\r
switch (*DataBits) {\r
- case 0:\r
- *DataBits = 8;\r
- case 8:\r
- LineControl |= PL011_UARTLCR_H_WLEN_8;\r
- break;\r
- case 7:\r
- LineControl |= PL011_UARTLCR_H_WLEN_7;\r
- break;\r
- case 6:\r
- LineControl |= PL011_UARTLCR_H_WLEN_6;\r
- break;\r
- case 5:\r
- LineControl |= PL011_UARTLCR_H_WLEN_5;\r
- break;\r
- default:\r
- return RETURN_INVALID_PARAMETER;\r
+ case 0:\r
+ *DataBits = 8;\r
+ case 8:\r
+ LineControl |= PL011_UARTLCR_H_WLEN_8;\r
+ break;\r
+ case 7:\r
+ LineControl |= PL011_UARTLCR_H_WLEN_7;\r
+ break;\r
+ case 6:\r
+ LineControl |= PL011_UARTLCR_H_WLEN_6;\r
+ break;\r
+ case 5:\r
+ LineControl |= PL011_UARTLCR_H_WLEN_5;\r
+ break;\r
+ default:\r
+ return RETURN_INVALID_PARAMETER;\r
}\r
\r
//\r
// Stop Bits\r
//\r
switch (*StopBits) {\r
- case DefaultStopBits:\r
- *StopBits = OneStopBit;\r
- case OneStopBit:\r
- // Nothing to do. One stop bit is enabled by default.\r
- break;\r
- case TwoStopBits:\r
- LineControl |= PL011_UARTLCR_H_STP2;\r
- break;\r
- case OneFiveStopBits:\r
+ case DefaultStopBits:\r
+ *StopBits = OneStopBit;\r
+ case OneStopBit:\r
+ // Nothing to do. One stop bit is enabled by default.\r
+ break;\r
+ case TwoStopBits:\r
+ LineControl |= PL011_UARTLCR_H_STP2;\r
+ break;\r
+ case OneFiveStopBits:\r
// Only 1 or 2 stop bits are supported\r
- default:\r
- return RETURN_INVALID_PARAMETER;\r
+ default:\r
+ return RETURN_INVALID_PARAMETER;\r
}\r
\r
// Don't send the LineControl value to the PL011 yet,\r
\r
// If PL011 Integer value has been defined then always ignore the BAUD rate\r
if (FixedPcdGet32 (PL011UartInteger) != 0) {\r
- Integer = FixedPcdGet32 (PL011UartInteger);\r
+ Integer = FixedPcdGet32 (PL011UartInteger);\r
Fractional = FixedPcdGet32 (PL011UartFractional);\r
} else {\r
// If BAUD rate is zero then replace it with the system default value\r
return RETURN_INVALID_PARAMETER;\r
}\r
}\r
+\r
if (0 == UartClkInHz) {\r
return RETURN_INVALID_PARAMETER;\r
}\r
\r
- Divisor = (UartClkInHz * 4) / *BaudRate;\r
- Integer = Divisor >> FRACTION_PART_SIZE_IN_BITS;\r
+ Divisor = (UartClkInHz * 4) / *BaudRate;\r
+ Integer = Divisor >> FRACTION_PART_SIZE_IN_BITS;\r
Fractional = Divisor & FRACTION_PART_MASK;\r
}\r
\r
// and re-initialize only if the settings are different.\r
//\r
if (((MmioRead32 (UartBase + UARTCR) & PL011_UARTCR_UARTEN) != 0) &&\r
- (MmioRead32 (UartBase + UARTLCR_H) == LineControl) &&\r
- (MmioRead32 (UartBase + UARTIBRD) == Integer) &&\r
- (MmioRead32 (UartBase + UARTFBRD) == Fractional)) {\r
+ (MmioRead32 (UartBase + UARTLCR_H) == LineControl) &&\r
+ (MmioRead32 (UartBase + UARTIBRD) == Integer) &&\r
+ (MmioRead32 (UartBase + UARTFBRD) == Fractional))\r
+ {\r
// Nothing to do - already initialized with correct attributes\r
return RETURN_SUCCESS;\r
}\r
\r
// Wait for the end of transmission\r
- while ((MmioRead32 (UartBase + UARTFR) & PL011_UARTFR_TXFE) == 0);\r
+ while ((MmioRead32 (UartBase + UARTFR) & PL011_UARTFR_TXFE) == 0) {\r
+ }\r
\r
// Disable UART: "The UARTLCR_H, UARTIBRD, and UARTFBRD registers must not be changed\r
// when the UART is enabled"\r
MmioWrite32 (UartBase + UARTECR, 0);\r
\r
// Enable Tx, Rx, and UART overall\r
- MmioWrite32 (UartBase + UARTCR,\r
- PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN);\r
+ MmioWrite32 (\r
+ UartBase + UARTCR,\r
+ PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN\r
+ );\r
\r
return RETURN_SUCCESS;\r
}\r
RETURN_STATUS\r
EFIAPI\r
PL011UartSetControl (\r
- IN UINTN UartBase,\r
- IN UINT32 Control\r
+ IN UINTN UartBase,\r
+ IN UINT32 Control\r
)\r
{\r
UINT32 Bits;\r
RETURN_STATUS\r
EFIAPI\r
PL011UartGetControl (\r
- IN UINTN UartBase,\r
- OUT UINT32 *Control\r
+ IN UINTN UartBase,\r
+ OUT UINT32 *Control\r
)\r
{\r
- UINT32 FlagRegister;\r
- UINT32 ControlRegister;\r
+ UINT32 FlagRegister;\r
+ UINT32 ControlRegister;\r
\r
-\r
- FlagRegister = MmioRead32 (UartBase + UARTFR);\r
+ FlagRegister = MmioRead32 (UartBase + UARTFR);\r
ControlRegister = MmioRead32 (UartBase + UARTCR);\r
\r
*Control = 0;\r
}\r
\r
if ((ControlRegister & (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN))\r
- == (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN)) {\r
+ == (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN))\r
+ {\r
*Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;\r
}\r
\r
UINTN\r
EFIAPI\r
PL011UartWrite (\r
- IN UINTN UartBase,\r
- IN UINT8 *Buffer,\r
- IN UINTN NumberOfBytes\r
+ IN UINTN UartBase,\r
+ IN UINT8 *Buffer,\r
+ IN UINTN NumberOfBytes\r
)\r
{\r
- UINT8* CONST Final = &Buffer[NumberOfBytes];\r
+ UINT8 *CONST Final = &Buffer[NumberOfBytes];\r
\r
while (Buffer < Final) {\r
// Wait until UART able to accept another char\r
- while ((MmioRead32 (UartBase + UARTFR) & UART_TX_FULL_FLAG_MASK));\r
+ while ((MmioRead32 (UartBase + UARTFR) & UART_TX_FULL_FLAG_MASK)) {\r
+ }\r
\r
MmioWrite8 (UartBase + UARTDR, *Buffer++);\r
}\r
UINTN\r
EFIAPI\r
PL011UartRead (\r
- IN UINTN UartBase,\r
- OUT UINT8 *Buffer,\r
- IN UINTN NumberOfBytes\r
+ IN UINTN UartBase,\r
+ OUT UINT8 *Buffer,\r
+ IN UINTN NumberOfBytes\r
)\r
{\r
- UINTN Count;\r
+ UINTN Count;\r
\r
for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {\r
- while ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) != 0);\r
+ while ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) != 0) {\r
+ }\r
+\r
*Buffer = MmioRead8 (UartBase + UARTDR);\r
}\r
\r
BOOLEAN\r
EFIAPI\r
PL011UartPoll (\r
- IN UINTN UartBase\r
+ IN UINTN UartBase\r
)\r
{\r
return ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) == 0);\r
projects / mirror_edk2.git / blobdiff