ArmPlatformPkg: Add ArmPlatformGetPlatformPpiList()

[mirror_edk2.git] / ArmPlatformPkg / PrePeiCore / MainMPCore.c

diff --git a/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
index 17a0002dee4d828f2ebd932c3f7b5d0c0a0aeeb0..25a11cf1bdfb6142e65dd0cd018d98346eb63ca3 100644 (file)
--- a/ArmPlatformPkg/PrePeiCore/MainMPCore.c
+++ b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
@@ -12,14 +12,12 @@
 *\r
 **/\r
 \r
+#include <Library/ArmGicLib.h>\r
 #include <Library/ArmMPCoreMailBoxLib.h>\r
 #include <Chipset/ArmV7.h>\r
-#include <Drivers/PL390Gic.h>\r
 \r
 #include "PrePeiCore.h"\r
 \r
-extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;\r
-\r
 /*\r
  * This is the main function for secondary cores. They loop around until a non Null value is written to\r
  * SYS_FLAGS register.The SYS_FLAGS register is platform specific.\r
@@ -32,7 +30,7 @@ extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;
 VOID\r
 EFIAPI\r
 SecondaryMain (\r
-  IN UINTN CoreId\r
+  IN UINTN MpId\r
   )\r
 {\r
   // Function pointer to Secondary Core entry point\r
@@ -45,7 +43,7 @@ SecondaryMain (
   while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {\r
     ArmCallWFI();\r
     // Acknowledge the interrupt and send End of Interrupt signal.\r
-    PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);\r
+    ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);\r
   }\r
 \r
   secondary_start = (VOID (*)())secondary_entry_addr;\r
@@ -64,31 +62,43 @@ PrimaryMain (
   )\r
 {\r
   EFI_SEC_PEI_HAND_OFF        SecCoreData;\r
+  UINTN                       PpiListSize;\r
+  EFI_PEI_PPI_DESCRIPTOR      *PpiList;\r
+  UINTN                       TemporaryRamBase;\r
+  UINTN                       TemporaryRamSize;\r
+\r
+  CreatePpiList (&PpiListSize, &PpiList);\r
 \r
-  //Enable the GIC Distributor\r
-  PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
+  // Enable the GIC Distributor\r
+  ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
 \r
   // If ArmVe has not been built as Standalone then we need to wake up the secondary cores\r
-  if (!PcdGet32(PcdStandalone)) {\r
+  if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {\r
     // Sending SGI to all the Secondary CPU interfaces\r
-    PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
+    ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
   }\r
 \r
+  // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at\r
+  // the base of the primary core stack\r
+  PpiListSize = ALIGN_VALUE(PpiListSize, 0x4);\r
+  TemporaryRamBase = (UINTN)PcdGet32 (PcdCPUCoresStackBase) + PpiListSize;\r
+  TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;\r
+\r
   //\r
   // Bind this information into the SEC hand-off state\r
   // Note: this must be in sync with the stuff in the asm file\r
   // Note also:  HOBs (pei temp ram) MUST be above stack\r
   //\r
   SecCoreData.DataSize               = sizeof(EFI_SEC_PEI_HAND_OFF);\r
-  SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress);\r
-  SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize);\r
-  SecCoreData.TemporaryRamBase       = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)\r
-  SecCoreData.TemporaryRamSize       = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);\r
-  SecCoreData.PeiTemporaryRamBase    = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));\r
+  SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdFvBaseAddress);\r
+  SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);\r
+  SecCoreData.TemporaryRamBase       = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)\r
+  SecCoreData.TemporaryRamSize       = TemporaryRamSize;\r
+  SecCoreData.PeiTemporaryRamBase    = SecCoreData.TemporaryRamBase;\r
   SecCoreData.PeiTemporaryRamSize    = SecCoreData.TemporaryRamSize / 2;\r
-  SecCoreData.StackBase              = SecCoreData.TemporaryRamBase;\r
-  SecCoreData.StackSize              = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;\r
+  SecCoreData.StackBase              = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize/2));\r
+  SecCoreData.StackSize              = SecCoreData.TemporaryRamSize / 2;\r
 \r
   // Jump to PEI core entry point\r
-  (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);\r
+  (PeiCoreEntryPoint)(&SecCoreData, PpiList);\r
 }\r