*\r
**/\r
\r
-#include <PiPei.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/PcdLib.h>\r
+#include <Library/ArmGicLib.h>\r
#include <Library/ArmMPCoreMailBoxLib.h>\r
#include <Chipset/ArmV7.h>\r
-#include <Drivers/PL390Gic.h>\r
\r
-extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;\r
+#include "PrePeiCore.h"\r
\r
/*\r
* This is the main function for secondary cores. They loop around until a non Null value is written to\r
*/\r
VOID\r
EFIAPI\r
-secondary_main(IN UINTN CoreId)\r
+SecondaryMain (\r
+ IN UINTN MpId\r
+ )\r
{\r
- //Function pointer to Secondary Core entry point\r
- VOID (*secondary_start)(VOID);\r
- UINTN secondary_entry_addr=0;\r
+ // Function pointer to Secondary Core entry point\r
+ VOID (*secondary_start)(VOID);\r
+ UINTN secondary_entry_addr=0;\r
\r
- //Clear Secondary cores MailBox\r
- ArmClearMPCoreMailbox();\r
+ // Clear Secondary cores MailBox\r
+ ArmClearMPCoreMailbox();\r
\r
- while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {\r
- ArmCallWFI();\r
- //Acknowledge the interrupt and send End of Interrupt signal.\r
- PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);\r
- }\r
+ while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {\r
+ ArmCallWFI();\r
+ // Acknowledge the interrupt and send End of Interrupt signal.\r
+ ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);\r
+ }\r
\r
- secondary_start = (VOID (*)())secondary_entry_addr;\r
+ secondary_start = (VOID (*)())secondary_entry_addr;\r
\r
- //Jump to secondary core entry point.\r
- secondary_start();\r
+ // Jump to secondary core entry point.\r
+ secondary_start();\r
\r
- //the secondaries shouldn't reach here\r
- ASSERT(FALSE);\r
+ // The secondaries shouldn't reach here\r
+ ASSERT(FALSE);\r
}\r
\r
-VOID primary_main (\r
+VOID\r
+EFIAPI\r
+PrimaryMain (\r
IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r
)\r
{\r
- EFI_SEC_PEI_HAND_OFF SecCoreData;\r
+ EFI_SEC_PEI_HAND_OFF SecCoreData;\r
+ UINTN PpiListSize;\r
+ EFI_PEI_PPI_DESCRIPTOR *PpiList;\r
+ UINTN TemporaryRamBase;\r
+ UINTN TemporaryRamSize;\r
+\r
+ CreatePpiList (&PpiListSize, &PpiList);\r
+\r
+ // Enable the GIC Distributor\r
+ ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
\r
- //Enable the GIC Distributor\r
- PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
+ // If ArmVe has not been built as Standalone then we need to wake up the secondary cores\r
+ if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {\r
+ // Sending SGI to all the Secondary CPU interfaces\r
+ ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
+ }\r
\r
- // If ArmVe has not been built as Standalone then we need to wake up the secondary cores\r
- if (FeaturePcdGet(PcdStandalone) == FALSE) {\r
- // Sending SGI to all the Secondary CPU interfaces\r
- PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
- }\r
+ // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at\r
+ // the base of the primary core stack\r
+ PpiListSize = ALIGN_VALUE(PpiListSize, 0x4);\r
+ TemporaryRamBase = (UINTN)PcdGet32 (PcdCPUCoresStackBase) + PpiListSize;\r
+ TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;\r
\r
- //\r
- // Bind this information into the SEC hand-off state\r
- // Note: this must be in sync with the stuff in the asm file\r
- // Note also: HOBs (pei temp ram) MUST be above stack\r
- //\r
- SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);\r
- SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdEmbeddedFdBaseAddress);\r
- SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdEmbeddedFdSize);\r
- SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)\r
- SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);\r
- SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));\r
- SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2;\r
- SecCoreData.StackBase = SecCoreData.TemporaryRamBase;\r
- SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;\r
+ //\r
+ // Bind this information into the SEC hand-off state\r
+ // Note: this must be in sync with the stuff in the asm file\r
+ // Note also: HOBs (pei temp ram) MUST be above stack\r
+ //\r
+ SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);\r
+ SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdFvBaseAddress);\r
+ SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);\r
+ SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)\r
+ SecCoreData.TemporaryRamSize = TemporaryRamSize;\r
+ SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;\r
+ SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2;\r
+ SecCoreData.StackBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize/2));\r
+ SecCoreData.StackSize = SecCoreData.TemporaryRamSize / 2;\r
\r
- // jump to pei core entry point\r
- (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);\r
+ // Jump to PEI core entry point\r
+ (PeiCoreEntryPoint)(&SecCoreData, PpiList);\r
}\r
projects / mirror_edk2.git / blobdiff