ARM Packages: Rename PcdNormal* into Pcd* PCDs

[mirror_edk2.git] / ArmPlatformPkg / PrePeiCore / MainMPCore.c

diff --git a/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
index 39de31a42aaa74829ee0258a3970f307be8afbc1..5402161b62b3fc9cd73a6f50c6fc016bdbf15aa3 100644 (file)
--- a/ArmPlatformPkg/PrePeiCore/MainMPCore.c
+++ b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
@@ -12,11 +12,9 @@
 *\r
 **/\r
 \r
-#include <Library/DebugLib.h>\r
-#include <Library/PcdLib.h>\r
+#include <Library/ArmGicLib.h>\r
 #include <Library/ArmMPCoreMailBoxLib.h>\r
 #include <Chipset/ArmV7.h>\r
-#include <Drivers/PL390Gic.h>\r
 \r
 #include "PrePeiCore.h"\r
 \r
@@ -34,7 +32,7 @@ extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;
 VOID\r
 EFIAPI\r
 SecondaryMain (\r
-  IN UINTN CoreId\r
+  IN UINTN MpId\r
   )\r
 {\r
   // Function pointer to Secondary Core entry point\r
@@ -47,7 +45,7 @@ SecondaryMain (
   while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {\r
     ArmCallWFI();\r
     // Acknowledge the interrupt and send End of Interrupt signal.\r
-    PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);\r
+    ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);\r
   }\r
 \r
   secondary_start = (VOID (*)())secondary_entry_addr;\r
@@ -67,13 +65,13 @@ PrimaryMain (
 {\r
   EFI_SEC_PEI_HAND_OFF        SecCoreData;\r
 \r
-  //Enable the GIC Distributor\r
-  PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
+  // Enable the GIC Distributor\r
+  ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
 \r
   // If ArmVe has not been built as Standalone then we need to wake up the secondary cores\r
-  if (FeaturePcdGet(PcdStandalone) == FALSE) {\r
+  if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {\r
     // Sending SGI to all the Secondary CPU interfaces\r
-    PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
+    ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
   }\r
 \r
   //\r
@@ -82,10 +80,10 @@ PrimaryMain (
   // Note also:  HOBs (pei temp ram) MUST be above stack\r
   //\r
   SecCoreData.DataSize               = sizeof(EFI_SEC_PEI_HAND_OFF);\r
-  SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress);\r
-  SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize);\r
-  SecCoreData.TemporaryRamBase       = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)\r
-  SecCoreData.TemporaryRamSize       = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);\r
+  SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdFvBaseAddress);\r
+  SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);\r
+  SecCoreData.TemporaryRamBase       = (VOID *)(UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize); // We consider we run on the primary core (and so we use the first stack)\r
+  SecCoreData.TemporaryRamSize       = (UINTN)(UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize);\r
   SecCoreData.PeiTemporaryRamBase    = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));\r
   SecCoreData.PeiTemporaryRamSize    = SecCoreData.TemporaryRamSize / 2;\r
   SecCoreData.StackBase              = SecCoreData.TemporaryRamBase;\r