ArmPlatformPkg: Updated the stack setup to have the same geometry between the Secure...

[mirror_edk2.git] / ArmPlatformPkg / PrePeiCore / MainMPCore.c

diff --git a/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
index 25a11cf1bdfb6142e65dd0cd018d98346eb63ca3..a98d560133eadd3707551a4984a3bded15347a0a 100644 (file)
--- a/ArmPlatformPkg/PrePeiCore/MainMPCore.c
+++ b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
@@ -1,6 +1,6 @@
 /** @file\r
 *\r
-*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
 *\r
 *  This program and the accompanying materials\r
 *  are licensed and made available under the terms and conditions of the BSD License\r
@@ -13,8 +13,8 @@
 **/\r
 \r
 #include <Library/ArmGicLib.h>\r
-#include <Library/ArmMPCoreMailBoxLib.h>\r
-#include <Chipset/ArmV7.h>\r
+\r
+#include <Ppi/ArmMpCoreInfo.h>\r
 \r
 #include "PrePeiCore.h"\r
 \r
@@ -33,23 +33,63 @@ SecondaryMain (
   IN UINTN MpId\r
   )\r
 {\r
-  // Function pointer to Secondary Core entry point\r
-  VOID (*secondary_start)(VOID);\r
-  UINTN secondary_entry_addr=0;\r
+  EFI_STATUS              Status;\r
+  UINTN                   PpiListSize;\r
+  UINTN                   PpiListCount;\r
+  EFI_PEI_PPI_DESCRIPTOR  *PpiList;\r
+  ARM_MP_CORE_INFO_PPI    *ArmMpCoreInfoPpi;\r
+  UINTN                   Index;\r
+  UINTN                   ArmCoreCount;\r
+  ARM_CORE_INFO           *ArmCoreInfoTable;\r
+  UINT32                  ClusterId;\r
+  UINT32                  CoreId;\r
+  VOID                    (*SecondaryStart)(VOID);\r
+  UINTN                   SecondaryEntryAddr;\r
+\r
+  ClusterId = GET_CLUSTER_ID(MpId);\r
+  CoreId    = GET_CORE_ID(MpId);\r
+\r
+  // Get the gArmMpCoreInfoPpiGuid\r
+  PpiListSize = 0;\r
+  ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);\r
+  PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);\r
+  for (Index = 0; Index < PpiListCount; Index++, PpiList++) {\r
+    if (CompareGuid (PpiList->Guid, &gArmMpCoreInfoPpiGuid) == TRUE) {\r
+      break;\r
+    }\r
+  }\r
+\r
+  // On MP Core Platform we must implement the ARM MP Core Info PPI\r
+  ASSERT (Index != PpiListCount);\r
+\r
+  ArmMpCoreInfoPpi = PpiList->Ppi;\r
+  ArmCoreCount = 0;\r
+  Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  // Find the core in the ArmCoreTable\r
+  for (Index = 0; Index < ArmCoreCount; Index++) {\r
+    if ((ArmCoreInfoTable[Index].ClusterId == ClusterId) && (ArmCoreInfoTable[Index].CoreId == CoreId)) {\r
+      break;\r
+    }\r
+  }\r
+\r
+  // The ARM Core Info Table must define every core\r
+  ASSERT (Index != ArmCoreCount);\r
 \r
   // Clear Secondary cores MailBox\r
-  ArmClearMPCoreMailbox();\r
+  MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);\r
 \r
-  while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {\r
-    ArmCallWFI();\r
+  SecondaryEntryAddr = 0;\r
+  while (SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress), SecondaryEntryAddr == 0) {\r
+    ArmCallWFI ();\r
     // Acknowledge the interrupt and send End of Interrupt signal.\r
     ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);\r
   }\r
 \r
-  secondary_start = (VOID (*)())secondary_entry_addr;\r
-\r
   // Jump to secondary core entry point.\r
-  secondary_start();\r
+  SecondaryStart = (VOID (*)())SecondaryEntryAddr;\r
+  SecondaryStart();\r
 \r
   // The secondaries shouldn't reach here\r
   ASSERT(FALSE);\r
@@ -84,6 +124,10 @@ PrimaryMain (
   TemporaryRamBase = (UINTN)PcdGet32 (PcdCPUCoresStackBase) + PpiListSize;\r
   TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;\r
 \r
+  // Make sure the size is 8-byte aligned. Once divided by 2, the size should be 4-byte aligned\r
+  // to ensure the stack pointer is 4-byte aligned.\r
+  TemporaryRamSize = TemporaryRamSize - (TemporaryRamSize & (0x8-1));\r
+\r
   //\r
   // Bind this information into the SEC hand-off state\r
   // Note: this must be in sync with the stuff in the asm file\r
@@ -96,8 +140,8 @@ PrimaryMain (
   SecCoreData.TemporaryRamSize       = TemporaryRamSize;\r
   SecCoreData.PeiTemporaryRamBase    = SecCoreData.TemporaryRamBase;\r
   SecCoreData.PeiTemporaryRamSize    = SecCoreData.TemporaryRamSize / 2;\r
-  SecCoreData.StackBase              = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize/2));\r
-  SecCoreData.StackSize              = SecCoreData.TemporaryRamSize / 2;\r
+  SecCoreData.StackBase              = (VOID *)ALIGN_VALUE((UINTN)(SecCoreData.TemporaryRamBase) + SecCoreData.PeiTemporaryRamSize, 0x4);\r
+  SecCoreData.StackSize              = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase;\r
 \r
   // Jump to PEI core entry point\r
   (PeiCoreEntryPoint)(&SecCoreData, PpiList);\r