/** @file\r
-*\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
+\r
+ Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
+\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
**/\r
\r
-#include <Library/DebugLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <Library/ArmMPCoreMailBoxLib.h>\r
-#include <Chipset/ArmV7.h>\r
-#include <Drivers/PL390Gic.h>\r
+#include <Library/ArmGicLib.h>\r
\r
-#include "PrePeiCore.h"\r
+#include <Ppi/ArmMpCoreInfo.h>\r
\r
-extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;\r
+#include "PrePeiCore.h"\r
\r
/*\r
* This is the main function for secondary cores. They loop around until a non Null value is written to\r
VOID\r
EFIAPI\r
SecondaryMain (\r
- IN UINTN CoreId\r
+ IN UINTN MpId\r
)\r
{\r
- // Function pointer to Secondary Core entry point\r
- VOID (*secondary_start)(VOID);\r
- UINTN secondary_entry_addr=0;\r
+ EFI_STATUS Status;\r
+ UINTN PpiListSize;\r
+ UINTN PpiListCount;\r
+ EFI_PEI_PPI_DESCRIPTOR *PpiList;\r
+ ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;\r
+ UINTN Index;\r
+ UINTN ArmCoreCount;\r
+ ARM_CORE_INFO *ArmCoreInfoTable;\r
+ UINT32 ClusterId;\r
+ UINT32 CoreId;\r
\r
- // Clear Secondary cores MailBox\r
- ArmClearMPCoreMailbox();\r
+ VOID (*SecondaryStart)(\r
+ VOID\r
+ );\r
+ UINTN SecondaryEntryAddr;\r
+ UINTN AcknowledgeInterrupt;\r
+ UINTN InterruptId;\r
\r
- while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {\r
- ArmCallWFI();\r
- // Acknowledge the interrupt and send End of Interrupt signal.\r
- PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);\r
+ ClusterId = GET_CLUSTER_ID (MpId);\r
+ CoreId = GET_CORE_ID (MpId);\r
+\r
+ // Get the gArmMpCoreInfoPpiGuid\r
+ PpiListSize = 0;\r
+ ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);\r
+ PpiListCount = PpiListSize / sizeof (EFI_PEI_PPI_DESCRIPTOR);\r
+ for (Index = 0; Index < PpiListCount; Index++, PpiList++) {\r
+ if (CompareGuid (PpiList->Guid, &gArmMpCoreInfoPpiGuid) == TRUE) {\r
+ break;\r
+ }\r
+ }\r
+\r
+ // On MP Core Platform we must implement the ARM MP Core Info PPI\r
+ ASSERT (Index != PpiListCount);\r
+\r
+ ArmMpCoreInfoPpi = PpiList->Ppi;\r
+ ArmCoreCount = 0;\r
+ Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ // Find the core in the ArmCoreTable\r
+ for (Index = 0; Index < ArmCoreCount; Index++) {\r
+ if ((GET_MPIDR_AFF1 (ArmCoreInfoTable[Index].Mpidr) == ClusterId) &&\r
+ (GET_MPIDR_AFF0 (ArmCoreInfoTable[Index].Mpidr) == CoreId))\r
+ {\r
+ break;\r
+ }\r
}\r
\r
- secondary_start = (VOID (*)())secondary_entry_addr;\r
+ // The ARM Core Info Table must define every core\r
+ ASSERT (Index != ArmCoreCount);\r
+\r
+ // Clear Secondary cores MailBox\r
+ MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);\r
+\r
+ do {\r
+ ArmCallWFI ();\r
+\r
+ // Read the Mailbox\r
+ SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);\r
+\r
+ // Acknowledge the interrupt and send End of Interrupt signal.\r
+ AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), &InterruptId);\r
+ // Check if it is a valid interrupt ID\r
+ if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet64 (PcdGicDistributorBase))) {\r
+ // Got a valid SGI number hence signal End of Interrupt\r
+ ArmGicEndOfInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);\r
+ }\r
+ } while (SecondaryEntryAddr == 0);\r
\r
// Jump to secondary core entry point.\r
- secondary_start();\r
+ SecondaryStart = (VOID (*)()) SecondaryEntryAddr;\r
+ SecondaryStart ();\r
\r
// The secondaries shouldn't reach here\r
- ASSERT(FALSE);\r
+ ASSERT (FALSE);\r
}\r
\r
VOID\r
IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r
)\r
{\r
- EFI_SEC_PEI_HAND_OFF SecCoreData;\r
+ EFI_SEC_PEI_HAND_OFF SecCoreData;\r
+ UINTN PpiListSize;\r
+ EFI_PEI_PPI_DESCRIPTOR *PpiList;\r
+ UINTN TemporaryRamBase;\r
+ UINTN TemporaryRamSize;\r
\r
- //Enable the GIC Distributor\r
- PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
+ CreatePpiList (&PpiListSize, &PpiList);\r
+\r
+ // Enable the GIC Distributor\r
+ ArmGicEnableDistributor (PcdGet64 (PcdGicDistributorBase));\r
\r
// If ArmVe has not been built as Standalone then we need to wake up the secondary cores\r
- if (!PcdGet32(PcdStandalone)) {\r
+ if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {\r
// Sending SGI to all the Secondary CPU interfaces\r
- PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
+ ArmGicSendSgiTo (PcdGet64 (PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r
}\r
\r
+ // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at\r
+ // the base of the primary core stack\r
+ PpiListSize = ALIGN_VALUE (PpiListSize, CPU_STACK_ALIGNMENT);\r
+ TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;\r
+ TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;\r
+\r
//\r
// Bind this information into the SEC hand-off state\r
// Note: this must be in sync with the stuff in the asm file\r
// Note also: HOBs (pei temp ram) MUST be above stack\r
//\r
- SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);\r
- SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress);\r
- SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize);\r
- SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)\r
- SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);\r
- SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));\r
- SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2;\r
- SecCoreData.StackBase = SecCoreData.TemporaryRamBase;\r
- SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;\r
+ SecCoreData.DataSize = sizeof (EFI_SEC_PEI_HAND_OFF);\r
+ SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);\r
+ SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);\r
+ SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)\r
+ SecCoreData.TemporaryRamSize = TemporaryRamSize;\r
+ SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;\r
+ SecCoreData.PeiTemporaryRamSize = ALIGN_VALUE (SecCoreData.TemporaryRamSize / 2, CPU_STACK_ALIGNMENT);\r
+ SecCoreData.StackBase = (VOID *)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);\r
+ SecCoreData.StackSize = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase;\r
\r
// Jump to PEI core entry point\r
- (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);\r
+ PeiCoreEntryPoint (&SecCoreData, PpiList);\r
}\r
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