MdeModulePkg/PciSioSerial: Fix bad EOL

[mirror_edk2.git] / ArmPlatformPkg / PrePi / MainMPCore.c

diff --git a/ArmPlatformPkg/PrePi/MainMPCore.c b/ArmPlatformPkg/PrePi/MainMPCore.c
index e8cd75186f811e611df1d4853682cb9de36dc932..27422d1f21b04ebedadc1648883640e8c0c2be08 100644 (file)
--- a/ArmPlatformPkg/PrePi/MainMPCore.c
+++ b/ArmPlatformPkg/PrePi/MainMPCore.c
@@ -1,6 +1,6 @@
 /** @file\r
 *\r
-*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
 *\r
 *  This program and the accompanying materials\r
 *  are licensed and made available under the terms and conditions of the BSD License\r
@@ -22,27 +22,19 @@ VOID
 PrimaryMain (\r
   IN  UINTN                     UefiMemoryBase,\r
   IN  UINTN                     StacksBase,\r
-  IN  UINTN                     GlobalVariableBase,\r
   IN  UINT64                    StartTimeStamp\r
   )\r
 {\r
-  // Check PcdGicPrimaryCoreId has been set in case the Primary Core is not the core 0 of Cluster 0\r
-  DEBUG_CODE_BEGIN();\r
-  if ((PcdGet32(PcdArmPrimaryCore) != 0) && (PcdGet32 (PcdGicPrimaryCoreId) == 0)) {\r
-    DEBUG((EFI_D_WARN,"Warning: the PCD PcdGicPrimaryCoreId does not seem to be set up for the configuration.\n"));\r
-  }\r
-  DEBUG_CODE_END();\r
-\r
   // Enable the GIC Distributor\r
-  ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
+  ArmGicEnableDistributor(PcdGet64(PcdGicDistributorBase));\r
 \r
   // In some cases, the secondary cores are waiting for an SGI from the next stage boot loader to resume their initialization\r
   if (!FixedPcdGet32(PcdSendSgiToBringUpSecondaryCores)) {\r
     // Sending SGI to all the Secondary CPU interfaces\r
-    ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r
+    ArmGicSendSgiTo (PcdGet64(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r
   }\r
 \r
-  PrePiMain (UefiMemoryBase, StacksBase, GlobalVariableBase, StartTimeStamp);\r
+  PrePiMain (UefiMemoryBase, StacksBase, StartTimeStamp);\r
 \r
   // We must never return\r
   ASSERT(FALSE);\r
@@ -62,6 +54,8 @@ SecondaryMain (
   UINT32                  CoreId;\r
   VOID                    (*SecondaryStart)(VOID);\r
   UINTN                   SecondaryEntryAddr;\r
+  UINTN                   AcknowledgeInterrupt;\r
+  UINTN                   InterruptId;\r
 \r
   ClusterId = GET_CLUSTER_ID(MpId);\r
   CoreId    = GET_CORE_ID(MpId);\r
@@ -94,7 +88,12 @@ SecondaryMain (
     SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);\r
 \r
     // Acknowledge the interrupt and send End of Interrupt signal.\r
-    ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase), NULL, NULL);\r
+    AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), &InterruptId);\r
+    // Check if it is a valid interrupt ID\r
+    if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet64 (PcdGicDistributorBase))) {\r
+      // Got a valid SGI number hence signal End of Interrupt\r
+      ArmGicEndOfInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);\r
+    }\r
   } while (SecondaryEntryAddr == 0);\r
 \r
   // Jump to secondary core entry point.\r