ArmPlatformPkg: Apply uncrustify changes

[mirror_edk2.git] / ArmPlatformPkg / PrePi / MainMPCore.c

diff --git a/ArmPlatformPkg/PrePi/MainMPCore.c b/ArmPlatformPkg/PrePi/MainMPCore.c
index 091464df2aa99db489d16fb97c5ffd460b0f7599..ce53cea6367cd75c760ae2eab51bc0bbb1c94d2e 100644 (file)
--- a/ArmPlatformPkg/PrePi/MainMPCore.c
+++ b/ArmPlatformPkg/PrePi/MainMPCore.c
@@ -14,52 +14,55 @@
 \r
 VOID\r
 PrimaryMain (\r
-  IN  UINTN                     UefiMemoryBase,\r
-  IN  UINTN                     StacksBase,\r
-  IN  UINT64                    StartTimeStamp\r
+  IN  UINTN   UefiMemoryBase,\r
+  IN  UINTN   StacksBase,\r
+  IN  UINT64  StartTimeStamp\r
   )\r
 {\r
   // Enable the GIC Distributor\r
-  ArmGicEnableDistributor(PcdGet64(PcdGicDistributorBase));\r
+  ArmGicEnableDistributor (PcdGet64 (PcdGicDistributorBase));\r
 \r
   // In some cases, the secondary cores are waiting for an SGI from the next stage boot loader to resume their initialization\r
-  if (!FixedPcdGet32(PcdSendSgiToBringUpSecondaryCores)) {\r
+  if (!FixedPcdGet32 (PcdSendSgiToBringUpSecondaryCores)) {\r
     // Sending SGI to all the Secondary CPU interfaces\r
-    ArmGicSendSgiTo (PcdGet64(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r
+    ArmGicSendSgiTo (PcdGet64 (PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r
   }\r
 \r
   PrePiMain (UefiMemoryBase, StacksBase, StartTimeStamp);\r
 \r
   // We must never return\r
-  ASSERT(FALSE);\r
+  ASSERT (FALSE);\r
 }\r
 \r
 VOID\r
 SecondaryMain (\r
-  IN  UINTN                     MpId\r
+  IN  UINTN  MpId\r
   )\r
 {\r
-  EFI_STATUS              Status;\r
-  ARM_MP_CORE_INFO_PPI    *ArmMpCoreInfoPpi;\r
-  UINTN                   Index;\r
-  UINTN                   ArmCoreCount;\r
-  ARM_CORE_INFO           *ArmCoreInfoTable;\r
-  UINT32                  ClusterId;\r
-  UINT32                  CoreId;\r
-  VOID                    (*SecondaryStart)(VOID);\r
-  UINTN                   SecondaryEntryAddr;\r
-  UINTN                   AcknowledgeInterrupt;\r
-  UINTN                   InterruptId;\r
-\r
-  ClusterId = GET_CLUSTER_ID(MpId);\r
-  CoreId    = GET_CORE_ID(MpId);\r
+  EFI_STATUS            Status;\r
+  ARM_MP_CORE_INFO_PPI  *ArmMpCoreInfoPpi;\r
+  UINTN                 Index;\r
+  UINTN                 ArmCoreCount;\r
+  ARM_CORE_INFO         *ArmCoreInfoTable;\r
+  UINT32                ClusterId;\r
+  UINT32                CoreId;\r
+\r
+  VOID  (*SecondaryStart)(\r
+    VOID\r
+    );\r
+  UINTN  SecondaryEntryAddr;\r
+  UINTN  AcknowledgeInterrupt;\r
+  UINTN  InterruptId;\r
+\r
+  ClusterId = GET_CLUSTER_ID (MpId);\r
+  CoreId    = GET_CORE_ID (MpId);\r
 \r
   // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)\r
-  Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi);\r
+  Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID **)&ArmMpCoreInfoPpi);\r
   ASSERT_EFI_ERROR (Status);\r
 \r
   ArmCoreCount = 0;\r
-  Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r
+  Status       = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r
   ASSERT_EFI_ERROR (Status);\r
 \r
   // Find the core in the ArmCoreTable\r
@@ -91,9 +94,9 @@ SecondaryMain (
   } while (SecondaryEntryAddr == 0);\r
 \r
   // Jump to secondary core entry point.\r
-  SecondaryStart = (VOID (*)())SecondaryEntryAddr;\r
-  SecondaryStart();\r
+  SecondaryStart = (VOID (*)()) SecondaryEntryAddr;\r
+  SecondaryStart ();\r
 \r
   // The secondaries shouldn't reach here\r
-  ASSERT(FALSE);\r
+  ASSERT (FALSE);\r
 }\r