ArmPkg/ArmLib.h: Removed GET_CORE_POS macro

[mirror_edk2.git] / ArmPlatformPkg / Sec / Sec.c

diff --git a/ArmPlatformPkg/Sec/Sec.c b/ArmPlatformPkg/Sec/Sec.c
index 52fa53a6475ac28cef14194a4348078639a753cd..015c1613c6d66e99d5e70244da323a21f73d965c 100644 (file)
--- a/ArmPlatformPkg/Sec/Sec.c
+++ b/ArmPlatformPkg/Sec/Sec.c
@@ -1,15 +1,15 @@
 /** @file\r
 *  Main file supporting the SEC Phase on ARM Platforms\r
 *\r
-*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-*  \r
-*  This program and the accompanying materials                          \r
-*  are licensed and made available under the terms and conditions of the BSD License         \r
-*  which accompanies this distribution.  The full text of the license may be found at        \r
-*  http://opensource.org/licenses/bsd-license.php                                            \r
+*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
 *\r
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+*  This program and the accompanying materials\r
+*  are licensed and made available under the terms and conditions of the BSD License\r
+*  which accompanies this distribution.  The full text of the license may be found at\r
+*  http://opensource.org/licenses/bsd-license.php\r
+*\r
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
 *\r
 **/\r
 \r
@@ -19,6 +19,7 @@
 #include <Library/BaseMemoryLib.h>\r
 #include <Library/SerialPortLib.h>\r
 #include <Library/ArmGicLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
 \r
 #include "SecInternal.h"\r
 \r
@@ -56,7 +57,7 @@ CEntryPoint (
   ArmPlatformSecInitialize (MpId);\r
 \r
   // Primary CPU clears out the SCU tag RAMs, secondaries wait\r
-  if (IS_PRIMARY_CORE(MpId) && (SecBootMode == ARM_SEC_COLD_BOOT)) {\r
+  if (ArmPlatformIsPrimaryCore (MpId) && (SecBootMode == ARM_SEC_COLD_BOOT)) {\r
     if (ArmIsMpCore()) {\r
       // Signal for the initial memory is configured (event: BOOT_MEM_INIT)\r
       ArmCallSEV ();\r
@@ -106,9 +107,13 @@ CEntryPoint (
             ((PcdGet32(PcdCPUCoresSecMonStackBase) != 0) && (PcdGet32(PcdCPUCoreSecMonStackSize) != 0)));\r
 \r
     // Enter Monitor Mode\r
-    enter_monitor_mode ((UINTN)TrustedWorldInitialization, MpId, SecBootMode, (VOID*)(PcdGet32(PcdCPUCoresSecMonStackBase) + (PcdGet32(PcdCPUCoreSecMonStackSize) * (GET_CORE_POS(MpId) + 1))));\r
+    enter_monitor_mode (\r
+      (UINTN)TrustedWorldInitialization, MpId, SecBootMode,\r
+      (VOID*) (PcdGet32 (PcdCPUCoresSecMonStackBase) +\r
+          (PcdGet32 (PcdCPUCoreSecMonStackSize) * (ArmPlatformGetCorePosition (MpId) + 1)))\r
+      );\r
   } else {\r
-    if (IS_PRIMARY_CORE(MpId)) {\r
+    if (ArmPlatformIsPrimaryCore (MpId)) {\r
       SerialPrint ("Trust Zone Configuration is disabled\n\r");\r
     }\r
 \r
@@ -147,7 +152,7 @@ TrustedWorldInitialization (
 \r
   // Setup the Trustzone Chipsets\r
   if (SecBootMode == ARM_SEC_COLD_BOOT) {\r
-    if (IS_PRIMARY_CORE(MpId)) {\r
+    if (ArmPlatformIsPrimaryCore (MpId)) {\r
       if (ArmIsMpCore()) {\r
         // Signal the secondary core the Security settings is done (event: EVENT_SECURE_INIT)\r
         ArmCallSEV ();\r
@@ -165,8 +170,8 @@ TrustedWorldInitialization (
   JumpAddress = PcdGet32 (PcdFvBaseAddress);\r
   ArmPlatformSecExtraAction (MpId, &JumpAddress);\r
 \r
-  // Write to CP15 Non-secure Access Control Register\r
-  ArmWriteNsacr (PcdGet32 (PcdArmNsacr));\r
+  // Initialize architecture specific security policy\r
+  ArmSecArchTrustzoneInit ();\r
 \r
   // CP15 Secure Configuration Register\r
   ArmWriteScr (PcdGet32 (PcdArmScr));\r