/** @file
-* Main file supporting the SEC Phase for Versatile Express
+* Main file supporting the SEC Phase on ARM Platforms
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
*
**/
-#include <Library/DebugLib.h>
#include <Library/DebugAgentLib.h>
#include <Library/PcdLib.h>
#include <Library/PrintLib.h>
-#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/ArmLib.h>
#include <Library/SerialPortLib.h>
#include <Library/ArmPlatformLib.h>
+#include <Library/ArmGicLib.h>
-#include <Chipset/ArmV7.h>
-#include <Drivers/PL390Gic.h>
-
-#define ARM_PRIMARY_CORE 0
+#include "SecInternal.h"
#define SerialPrint(txt) SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1);
extern VOID *monitor_vector_table;
-VOID
-ArmSetupGicNonSecure (
- IN INTN GicDistributorBase,
- IN INTN GicInterruptInterfaceBase
-);
-
-// Vector Table for Sec Phase
-VOID
-SecVectorTable (
- VOID
- );
-
-VOID
-NonSecureWaitForFirmware (
- VOID
- );
-
-VOID
-enter_monitor_mode(
- IN VOID* Stack
- );
-
-VOID
-return_from_exception (
- IN UINTN NonSecureBase
- );
-
-VOID
-copy_cpsr_into_spsr (
- VOID
- );
-
VOID
CEntryPoint (
- IN UINTN CoreId
+ IN UINTN MpId
)
{
CHAR8 Buffer[100];
UINTN JumpAddress;
// Primary CPU clears out the SCU tag RAMs, secondaries wait
- if (CoreId == ARM_PRIMARY_CORE) {
+ if (IS_PRIMARY_CORE(MpId)) {
if (FixedPcdGet32(PcdMPCoreSupport)) {
- ArmInvalidScu();
+ ArmInvalidScu ();
}
// SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib
// Invalidate the data cache. Doesn't have to do the Data cache clean.
ArmInvalidateDataCache();
- //Invalidate Instruction Cache
+ // Invalidate Instruction Cache
ArmInvalidateInstructionCache();
- //Invalidate I & D TLBs
+ // Invalidate I & D TLBs
ArmInvalidateInstructionAndDataTlb();
// Enable Full Access to CoProcessors
ArmWriteCPACR (CPACR_CP_FULL_ACCESS);
// Enable SWP instructions
- ArmEnableSWPInstruction();
+ ArmEnableSWPInstruction ();
// Enable program flow prediction, if supported.
- ArmEnableBranchPrediction();
+ ArmEnableBranchPrediction ();
if (FixedPcdGet32(PcdVFPEnabled)) {
ArmEnableVFP();
}
- if (CoreId == ARM_PRIMARY_CORE) {
+ if (IS_PRIMARY_CORE(MpId)) {
// Initialize peripherals that must be done at the early stage
// Example: Some L2x0 controllers must be initialized in Secure World
ArmPlatformSecInitialize ();
}
// Test if Trustzone is supported on this platform
- if (ArmPlatformTrustzoneSupported()) {
+ if (ArmPlatformTrustzoneSupported ()) {
+ // Ensure the Monitor Stack Base & Size have been set
+ ASSERT(PcdGet32(PcdCPUCoresSecMonStackBase) != 0);
+ ASSERT(PcdGet32(PcdCPUCoreSecMonStackSize) != 0);
+
if (FixedPcdGet32(PcdMPCoreSupport)) {
// Setup SMP in Non Secure world
- ArmSetupSmpNonSecure (CoreId);
+ ArmSetupSmpNonSecure (GET_CORE_ID(MpId));
}
// Enter Monitor Mode
- enter_monitor_mode((VOID*)(PcdGet32(PcdCPUCoresSecMonStackBase) + (PcdGet32(PcdCPUCoreSecMonStackSize) * CoreId)));
+ enter_monitor_mode ((VOID*)(PcdGet32(PcdCPUCoresSecMonStackBase) + (PcdGet32(PcdCPUCoreSecMonStackSize) * GET_CORE_POS(MpId))));
//Write the monitor mode vector table address
ArmWriteVMBar((UINT32) &monitor_vector_table);
//-------------------- Monitor Mode ---------------------
// Setup the Trustzone Chipsets
- if (CoreId == ARM_PRIMARY_CORE) {
- ArmPlatformTrustzoneInit();
+ if (IS_PRIMARY_CORE(MpId)) {
+ ArmPlatformTrustzoneInit ();
// Wake up the secondary cores by sending a interrupt to everyone else
// NOTE 1: The Software Generated Interrupts are always enabled on Cortex-A9
// 3: As all the cores are in secure state, use secure SGI's
//
- PL390GicEnableDistributor (PcdGet32(PcdGicDistributorBase));
- PL390GicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
+ ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
+ ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
// Send SGI to all Secondary core to wake them up from WFI state.
- PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
+ ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
} else {
// The secondary cores need to wait until the Trustzone chipsets configuration is done
// before switching to Non Secure World
// Enabled GIC CPU Interface
- PL390GicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
+ ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
// Waiting for the SGI from the primary core
ArmCallWFI();
// Acknowledge the interrupt and send End of Interrupt signal.
- PL390GicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), ARM_PRIMARY_CORE);
+ ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
}
// Transfer the interrupt to Non-secure World
- PL390GicSetupNonSecure (PcdGet32(PcdGicDistributorBase),PcdGet32(PcdGicInterruptInterfaceBase));
+ ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase),PcdGet32(PcdGicInterruptInterfaceBase));
// Write to CP15 Non-secure Access Control Register :
// - Enable CP10 and CP11 accesses in NS World
// - Enable Access to Preload Engine in NS World
// - Enable lockable TLB entries allocation in NS world
// - Enable R/W access to SMP bit of Auxiliary Control Register in NS world
- ArmWriteNsacr(NSACR_NS_SMP | NSACR_TL | NSACR_PLE | NSACR_CP(10) | NSACR_CP(11));
+ ArmWriteNsacr (NSACR_NS_SMP | NSACR_TL | NSACR_PLE | NSACR_CP(10) | NSACR_CP(11));
// CP15 Secure Configuration Register with Non Secure bit (SCR_NS), CPSR.A modified in any
// security state (SCR_AW), CPSR.F modified in any security state (SCR_FW)
- ArmWriteScr(SCR_NS | SCR_FW | SCR_AW);
+ ArmWriteScr (SCR_NS | SCR_FW | SCR_AW);
} else {
- if (CoreId == ARM_PRIMARY_CORE) {
+ if (IS_PRIMARY_CORE(MpId)) {
SerialPrint ("Trust Zone Configuration is disabled\n\r");
}
// Trustzone is not enabled, just enable the Distributor and CPU interface
- if (CoreId == ARM_PRIMARY_CORE) {
- PL390GicEnableDistributor (PcdGet32(PcdGicDistributorBase));
+ if (IS_PRIMARY_CORE(MpId)) {
+ ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
}
- PL390GicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
+ ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
// With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
// If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
copy_cpsr_into_spsr ();
}
- JumpAddress = PcdGet32 (PcdNormalFvBaseAddress);
- ArmPlatformSecExtraAction (CoreId, &JumpAddress);
+ JumpAddress = PcdGet32 (PcdFvBaseAddress);
+ ArmPlatformSecExtraAction (MpId, &JumpAddress);
return_from_exception (JumpAddress);
//-------------------- Non Secure Mode ---------------------