**/
#include <Library/DebugLib.h>
+#include <Library/DebugAgentLib.h>
#include <Library/PcdLib.h>
#include <Library/PrintLib.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/ArmLib.h>
-#include <Chipset/ArmV7.h>
-#include <Drivers/PL390Gic.h>
-#include <Library/L2X0CacheLib.h>
#include <Library/SerialPortLib.h>
#include <Library/ArmPlatformLib.h>
-#define SerialPrint(txt) SerialPortWrite (txt, AsciiStrLen(txt)+1);
+#include <Chipset/ArmV7.h>
+#include <Drivers/PL390Gic.h>
+
+#define ARM_PRIMARY_CORE 0
+
+#define SerialPrint(txt) SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1);
extern VOID *monitor_vector_table;
-VOID ArmSetupGicNonSecure (
- IN INTN GicDistributorBase,
- IN INTN GicInterruptInterfaceBase
+VOID
+ArmSetupGicNonSecure (
+ IN INTN GicDistributorBase,
+ IN INTN GicInterruptInterfaceBase
);
// Vector Table for Sec Phase
-VOID SecVectorTable (VOID);
+VOID
+SecVectorTable (
+ VOID
+ );
-VOID NonSecureWaitForFirmware (
+VOID
+NonSecureWaitForFirmware (
VOID
);
{
CHAR8 Buffer[100];
UINTN CharCount;
+ UINTN JumpAddress;
// Primary CPU clears out the SCU tag RAMs, secondaries wait
- if (CoreId == 0) {
+ if (CoreId == ARM_PRIMARY_CORE) {
if (FixedPcdGet32(PcdMPCoreSupport)) {
ArmInvalidScu();
}
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware built at %a on %a\n\r",__TIME__, __DATE__);
SerialPortWrite ((UINT8 *) Buffer, CharCount);
+ // Initialize the Debug Agent for Source Level Debugging
+ InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL);
+ SaveAndSetDebugTimerInterrupt (TRUE);
+
// Now we've got UART, make the check:
// - The Vector table must be 32-byte aligned
ASSERT(((UINT32)SecVectorTable & ((1 << 5)-1)) == 0);
ArmEnableVFP();
}
- if (CoreId == 0) {
- // Initialize L2X0 but not enabled
- L2x0CacheInit(PcdGet32(PcdL2x0ControllerBase), FALSE);
+ if (CoreId == ARM_PRIMARY_CORE) {
+ // Initialize peripherals that must be done at the early stage
+ // Example: Some L2x0 controllers must be initialized in Secure World
+ ArmPlatformSecInitialize ();
// If we skip the PEI Core we could want to initialize the DRAM in the SEC phase.
// If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM
- if (FeaturePcdGet(PcdSkipPeiCore) || !FeaturePcdGet(PcdStandalone)) {
+ if (FeaturePcdGet(PcdSystemMemoryInitializeInSec)) {
// Initialize system memory (DRAM)
- ArmPlatformInitializeSystemMemory();
+ ArmPlatformInitializeSystemMemory ();
}
- // Turn Off NOR flash remapping to 0. We can will now see DRAM in low memory
- ArmPlatformBootRemapping();
+ // Some platform can change their physical memory mapping
+ ArmPlatformBootRemapping ();
}
// Test if Trustzone is supported on this platform
if (ArmPlatformTrustzoneSupported()) {
if (FixedPcdGet32(PcdMPCoreSupport)) {
// Setup SMP in Non Secure world
- ArmSetupSmpNonSecure(CoreId);
+ ArmSetupSmpNonSecure (CoreId);
}
// Enter Monitor Mode
ArmWriteVMBar((UINT32) &monitor_vector_table);
//-------------------- Monitor Mode ---------------------
- // setup the Trustzone Chipsets
- if (CoreId == 0) {
+ // Setup the Trustzone Chipsets
+ if (CoreId == ARM_PRIMARY_CORE) {
ArmPlatformTrustzoneInit();
// Wake up the secondary cores by sending a interrupt to everyone else
//
PL390GicEnableDistributor (PcdGet32(PcdGicDistributorBase));
- PL390GicEnableInterruptInterface(PcdGet32(PcdGicInterruptInterfaceBase));
+ PL390GicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
// Send SGI to all Secondary core to wake them up from WFI state.
PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
} else {
// The secondary cores need to wait until the Trustzone chipsets configuration is done
- // before swtching to Non Secure World
+ // before switching to Non Secure World
// Enabled GIC CPU Interface
PL390GicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
// Waiting for the SGI from the primary core
ArmCallWFI();
- //Acknowledge the interrupt and send End of Interrupt signal.
- PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);
+ // Acknowledge the interrupt and send End of Interrupt signal.
+ PL390GicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), ARM_PRIMARY_CORE);
}
// Transfer the interrupt to Non-secure World
- PL390GicSetupNonSecure(PcdGet32(PcdGicDistributorBase),PcdGet32(PcdGicInterruptInterfaceBase));
+ PL390GicSetupNonSecure (PcdGet32(PcdGicDistributorBase),PcdGet32(PcdGicInterruptInterfaceBase));
// Write to CP15 Non-secure Access Control Register :
// - Enable CP10 and CP11 accesses in NS World
// security state (SCR_AW), CPSR.F modified in any security state (SCR_FW)
ArmWriteScr(SCR_NS | SCR_FW | SCR_AW);
} else {
- if(0 == CoreId){
+ if (CoreId == ARM_PRIMARY_CORE) {
SerialPrint ("Trust Zone Configuration is disabled\n\r");
}
- //Trustzone is not enabled, just enable the Distributor and CPU interface
- PL390GicEnableInterruptInterface(PcdGet32(PcdGicInterruptInterfaceBase));
+ // Trustzone is not enabled, just enable the Distributor and CPU interface
+ if (CoreId == ARM_PRIMARY_CORE) {
+ PL390GicEnableDistributor (PcdGet32(PcdGicDistributorBase));
+ }
+ PL390GicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
// With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
// If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
// Status Register as the the current one (CPSR).
- copy_cpsr_into_spsr();
+ copy_cpsr_into_spsr ();
}
- // If ArmVe has not been built as Standalone then we need to patch the DRAM to add an infinite loop at the start address
- if (FeaturePcdGet(PcdStandalone) == FALSE) {
- if (CoreId == 0) {
- UINTN* StartAddress = (UINTN*)PcdGet32(PcdNormalFdBaseAddress);
+ JumpAddress = PcdGet32 (PcdNormalFvBaseAddress);
+ ArmPlatformSecExtraAction (CoreId, &JumpAddress);
- // Patch the DRAM to make an infinite loop at the start address
- *StartAddress = 0xEAFFFFFE; // opcode for while(1)
-
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Waiting for firmware at 0x%08X ...\n\r",StartAddress);
- SerialPortWrite ((UINT8 *) Buffer, CharCount);
-
- // To enter into Non Secure state, we need to make a return from exception
- return_from_exception(PcdGet32(PcdNormalFdBaseAddress));
- } else {
- // When the primary core is stopped by the hardware debugger to copy the firmware
- // into DRAM. The secondary cores are still running. As soon as the first bytes of
- // the firmware are written into DRAM, the secondary cores will start to execute the
- // code even if the firmware is not entirely written into the memory.
- // That's why the secondary cores need to be parked in WFI and wake up once the
- // firmware is ready.
-
- // Enter Secondary Cores into non Secure State. To enter into Non Secure state, we need to make a return from exception
- return_from_exception((UINTN)NonSecureWaitForFirmware);
- }
- } else {
- // To enter into Non Secure state, we need to make a return from exception
- return_from_exception(PcdGet32(PcdNormalFdBaseAddress));
- }
+ return_from_exception (JumpAddress);
//-------------------- Non Secure Mode ---------------------
// PEI Core should always load and never return
ASSERT (FALSE);
}
-// When the firmware is built as not Standalone, the secondary cores need to wait the firmware
-// entirely written into DRAM. It is the firmware from DRAM which will wake up the secondary cores.
-VOID NonSecureWaitForFirmware() {
- VOID (*secondary_start)(VOID);
-
- // The secondary cores will execute the fimrware once wake from WFI.
- secondary_start = (VOID (*)())PcdGet32(PcdNormalFdBaseAddress);
-
- ArmCallWFI();
-
- //Acknowledge the interrupt and send End of Interrupt signal.
- PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);
-
- //Jump to secondary core entry point.
- secondary_start();
-
- // PEI Core should always load and never return
- ASSERT (FALSE);
-}
-
VOID
SecCommonExceptionEntry (
IN UINT32 Entry,
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