- //-------------------- Monitor Mode ---------------------
- // Setup the Trustzone Chipsets
- if (IS_PRIMARY_CORE(MpId)) {
- ArmPlatformTrustzoneInit ();
-
- // Waiting for the Primary Core to have finished to initialize the Secure World
- ArmCpuSynchronizeSignal (ARM_CPU_EVENT_SECURE_INIT);
- } else {
- // The secondary cores need to wait until the Trustzone chipsets configuration is done
- // before switching to Non Secure World
-
- // Waiting for the Primary Core to have finished to initialize the Secure World
- ArmCpuSynchronizeWait (ARM_CPU_EVENT_SECURE_INIT);
- }
-
- // Transfer the interrupt to Non-secure World
- ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase));
-
- // Write to CP15 Non-secure Access Control Register :
- // - Enable CP10 and CP11 accesses in NS World
- // - Enable Access to Preload Engine in NS World
- // - Enable lockable TLB entries allocation in NS world
- // - Enable R/W access to SMP bit of Auxiliary Control Register in NS world
- ArmWriteNsacr (NSACR_NS_SMP | NSACR_TL | NSACR_PLE | NSACR_CP(10) | NSACR_CP(11));
-
- // CP15 Secure Configuration Register with Non Secure bit (SCR_NS), CPSR.A modified in any
- // security state (SCR_AW), CPSR.F modified in any security state (SCR_FW)
- ArmWriteScr (SCR_NS | SCR_FW | SCR_AW);