//\r
-// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
// \r
// This program and the accompanying materials \r
// are licensed and made available under the terms and conditions of the BSD License \r
\r
#include <AutoGen.h>\r
#include <AsmMacroIoLib.h>\r
-#include <Base.h>\r
-#include <Library/PcdLib.h>\r
-#include <Library/ArmPlatformLib.h>\r
+#include "SecInternal.h"\r
\r
.text\r
.align 3\r
\r
-GCC_ASM_EXPORT(_ModuleEntryPoint)\r
-\r
GCC_ASM_IMPORT(CEntryPoint)\r
GCC_ASM_IMPORT(ArmPlatformSecBootAction)\r
-GCC_ASM_IMPORT(ArmPlatformInitializeBootMemory)\r
+GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit)\r
GCC_ASM_IMPORT(ArmDisableInterrupts)\r
GCC_ASM_IMPORT(ArmDisableCachesAndMmu)\r
GCC_ASM_IMPORT(ArmWriteVBar)\r
GCC_ASM_IMPORT(ArmReadMpidr)\r
GCC_ASM_IMPORT(SecVectorTable)\r
-\r
-#if (FixedPcdGet32(PcdMPCoreSupport))\r
-GCC_ASM_IMPORT(ArmIsScuEnable)\r
-#endif\r
+GCC_ASM_IMPORT(ArmCallWFE)\r
+GCC_ASM_EXPORT(_ModuleEntryPoint)\r
\r
StartupAddr: .word ASM_PFX(CEntryPoint)\r
-SecVectorTableAddr: .word ASM_PFX(SecVectorTable)\r
\r
ASM_PFX(_ModuleEntryPoint):\r
// First ensure all interrupts are disabled\r
blx ASM_PFX(ArmPlatformSecBootAction)\r
\r
// Set VBAR to the start of the exception vectors in Secure Mode\r
- ldr r0, =SecVectorTable\r
+ LoadConstantToReg (ASM_PFX(SecVectorTable), r0)\r
bl ASM_PFX(ArmWriteVBar)\r
\r
_IdentifyCpu:\r
and r5, r0, r1\r
\r
// Is it the Primary Core ?\r
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r1)\r
- cmp r5, r1\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)\r
+ cmp r5, r3\r
// Only the primary core initialize the memory (SMC)\r
beq _InitMem\r
\r
-#if (FixedPcdGet32(PcdMPCoreSupport))\r
- // ... The secondary cores wait for SCU to be enabled\r
-_WaitForEnabledScu:\r
- bl ASM_PFX(ArmIsScuEnable)\r
- tst r1, #1\r
- beq _WaitForEnabledScu\r
+_WaitInitMem:\r
+ // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)\r
+ bl ASM_PFX(ArmCallWFE)\r
+ // Now the Init Mem is initialized, we setup the secondary core stacks\r
b _SetupSecondaryCoreStack\r
-#endif\r
\r
_InitMem:\r
// Initialize Init Boot Memory\r
- bl ASM_PFX(ArmPlatformInitializeBootMemory)\r
+ bl ASM_PFX(ArmPlatformSecBootMemoryInit)\r
\r
// Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)\r
LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)\r
\r
_SetupPrimaryCoreStack:\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r2)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r3)\r
- // Calculate the Top of the Stack\r
- add r2, r2, r3\r
- LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r3)\r
+ // Get the top of the primary stacks (and the base of the secondary stacks)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r
+ add r1, r1, r2\r
+\r
+ LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r2)\r
\r
// The reserved space for global variable must be 8-bytes aligned for pushing\r
// 64-bit variable on the stack\r
- SetPrimaryStack (r2, r3, r1)\r
-\r
- // Set all the SEC global variables to 0\r
- mov r3, sp\r
- mov r1, #0x0\r
-_InitGlobals:\r
- str r1, [r3], #4\r
- cmp r3, r2\r
- blt _InitGlobals\r
-\r
+ SetPrimaryStack (r1, r2, r3)\r
b _PrepareArguments\r
\r
_SetupSecondaryCoreStack:\r
- // Get the Core Position (ClusterId * 4) + CoreId\r
- GetCorePositionInStack(r0, r5, r1)\r
- // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
- add r0, r0, #1\r
-\r
- // Get the base of the stack for the secondary cores\r
+ // Get the top of the primary stacks (and the base of the secondary stacks)\r
LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r
add r1, r1, r2\r
\r
+ // Get the Core Position (ClusterId * 4) + CoreId\r
+ GetCorePositionInStack(r0, r5, r2)\r
+ // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
+ add r0, r0, #1\r
+\r
// StackOffset = CorePos * StackSize\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)\r
mul r0, r0, r2\r
// SP = StackBase + StackOffset\r
add sp, r1, r0\r
\r
-\r
_PrepareArguments:\r
// Move sec startup address into a data register\r
// Ensure we're jumping to FV version of the code (not boot remapped alias)\r