-#------------------------------------------------------------------------------
-#
-# ARM VE Entry point. Reset vector in FV header will brach to
-# _ModuleEntryPoint.
-#
-# Copyright (c) 2011, ARM Limited. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
-
-#include <AsmMacroIoLib.h>
-#include <Base.h>
-#include <Library/PcdLib.h>
-#include <Library/ArmPlatformLib.h>
-#include <AutoGen.h>
-
-#Start of Code section
-.text
-.align 3
-
-#make _ModuleEntryPoint as global
-GCC_ASM_EXPORT(_ModuleEntryPoint)
-
-#global functions referenced by this module
-GCC_ASM_IMPORT(CEntryPoint)
-GCC_ASM_IMPORT(ArmPlatformIsMemoryInitialized)
-GCC_ASM_IMPORT(ArmPlatformInitializeBootMemory)
-GCC_ASM_IMPORT(ArmDisableInterrupts)
-GCC_ASM_IMPORT(ArmDisableCachesAndMmu)
-GCC_ASM_IMPORT(ArmWriteVBar)
-GCC_ASM_IMPORT(SecVectorTable)
-
-#if (FixedPcdGet32(PcdMPCoreSupport))
-GCC_ASM_IMPORT(ArmIsScuEnable)
-#endif
-
-StartupAddr: .word ASM_PFX(CEntryPoint)
-SecVectorTableAddr: .word ASM_PFX(SecVectorTable)
-
-ASM_PFX(_ModuleEntryPoint):
- #Set VBAR to the start of the exception vectors in Secure Mode
- ldr r0, SecVectorTableAddr
- bl ASM_PFX(ArmWriteVBar)
-
- # First ensure all interrupts are disabled
- bl ASM_PFX(ArmDisableInterrupts)
-
- # Ensure that the MMU and caches are off
- bl ASM_PFX(ArmDisableCachesAndMmu)
-
-_IdentifyCpu:
- # Identify CPU ID
- bl ASM_PFX(ArmReadMpidr)
- and r5, r0, #0xf
-
- #get ID of this CPU in Multicore system
- cmp r5, #0
- # Only the primary core initialize the memory (SMC)
- beq _InitMem
-
-#if (FixedPcdGet32(PcdMPCoreSupport))
- # ... The secondary cores wait for SCU to be enabled
-_WaitForEnabledScu:
- bl ASM_PFX(ArmIsScuEnable)
- tst r1, #1
- beq _WaitForEnabledScu
- b _SetupStack
-#endif
-
-_InitMem:
- bl ASM_PFX(ArmPlatformIsMemoryInitialized)
- bne _SetupStack
-
- # Initialize Init Memory
- bl ASM_PFX(ArmPlatformInitializeBootMemory)
-
- # Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
- mov r5, #0
-
-_SetupStack:
- # Setup Stack for the 4 CPU cores
- #Read Stack Base address from PCD
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
-
- #read Stack size from PCD
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecStackSize), r2)
-
- #calcuate Stack Pointer reg value using Stack size and CPU ID.
- mov r3,r5 @ r3 = core_id
- mul r3,r3,r2 @ r3 = core_id * stack_size = offset from the stack base
- add r3,r3,r1 @ r3 ldr= stack_base + offset
- mov sp, r3
-
- # move sec startup address into a data register
- # ensure we're jumping to FV version of the code (not boot remapped alias)
- ldr r3, StartupAddr
-
- # Move the CoreId in r0 to be the first argument of the SEC Entry Point
- mov r0, r5
-
- # jump to SEC C code
- # r0 = core_id
- blx r3
-
-
+//\r
+// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+// \r
+// This program and the accompanying materials \r
+// are licensed and made available under the terms and conditions of the BSD License \r
+// which accompanies this distribution. The full text of the license may be found at \r
+// http://opensource.org/licenses/bsd-license.php \r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+//\r
+//\r
+\r
+#include <AutoGen.h>\r
+#include <AsmMacroIoLib.h>\r
+#include "SecInternal.h"\r
+\r
+.text\r
+.align 3\r
+\r
+GCC_ASM_IMPORT(CEntryPoint)\r
+GCC_ASM_IMPORT(ArmPlatformSecBootAction)\r
+GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit)\r
+GCC_ASM_IMPORT(ArmDisableInterrupts)\r
+GCC_ASM_IMPORT(ArmDisableCachesAndMmu)\r
+GCC_ASM_IMPORT(ArmWriteVBar)\r
+GCC_ASM_IMPORT(ArmReadMpidr)\r
+GCC_ASM_IMPORT(SecVectorTable)\r
+GCC_ASM_IMPORT(ArmCallWFE)\r
+GCC_ASM_EXPORT(_ModuleEntryPoint)\r
+\r
+StartupAddr: .word ASM_PFX(CEntryPoint)\r
+\r
+ASM_PFX(_ModuleEntryPoint):\r
+ // First ensure all interrupts are disabled\r
+ bl ASM_PFX(ArmDisableInterrupts)\r
+\r
+ // Ensure that the MMU and caches are off\r
+ bl ASM_PFX(ArmDisableCachesAndMmu)\r
+\r
+ // Jump to Platform Specific Boot Action function\r
+ blx ASM_PFX(ArmPlatformSecBootAction)\r
+\r
+ // Set VBAR to the start of the exception vectors in Secure Mode\r
+ LoadConstantToReg (ASM_PFX(SecVectorTable), r0)\r
+ bl ASM_PFX(ArmWriteVBar)\r
+\r
+_IdentifyCpu:\r
+ // Identify CPU ID\r
+ bl ASM_PFX(ArmReadMpidr)\r
+ // Get ID of this CPU in Multicore system\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
+ and r5, r0, r1\r
+ \r
+ // Is it the Primary Core ?\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)\r
+ cmp r5, r3\r
+ // Only the primary core initialize the memory (SMC)\r
+ beq _InitMem\r
+ \r
+_WaitInitMem:\r
+ // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)\r
+ bl ASM_PFX(ArmCallWFE)\r
+ // Now the Init Mem is initialized, we setup the secondary core stacks\r
+ b _SetupSecondaryCoreStack\r
+ \r
+_InitMem:\r
+ // Initialize Init Boot Memory\r
+ bl ASM_PFX(ArmPlatformSecBootMemoryInit)\r
+ \r
+ // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)\r
+\r
+_SetupPrimaryCoreStack:\r
+ // Get the top of the primary stacks (and the base of the secondary stacks)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r
+ add r1, r1, r2\r
+\r
+ LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r2)\r
+\r
+ // The reserved space for global variable must be 8-bytes aligned for pushing\r
+ // 64-bit variable on the stack\r
+ SetPrimaryStack (r1, r2, r3)\r
+ b _PrepareArguments\r
+\r
+_SetupSecondaryCoreStack:\r
+ // Get the top of the primary stacks (and the base of the secondary stacks)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r
+ add r1, r1, r2\r
+\r
+ // Get the Core Position (ClusterId * 4) + CoreId\r
+ GetCorePositionInStack(r0, r5, r2)\r
+ // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
+ add r0, r0, #1\r
+\r
+ // StackOffset = CorePos * StackSize\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)\r
+ mul r0, r0, r2\r
+ // SP = StackBase + StackOffset\r
+ add sp, r1, r0\r
+\r
+_PrepareArguments:\r
+ // Move sec startup address into a data register\r
+ // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
+ ldr r3, StartupAddr\r
+ \r
+ // Jump to SEC C code\r
+ // r0 = mp_id\r
+ mov r0, r5\r
+ blx r3\r
+ \r
+_NeverReturn:\r
+ b _NeverReturn\r