-#------------------------------------------------------------------------------ \r
-#\r
-# ARM VE Entry point. Reset vector in FV header will brach to\r
-# _ModuleEntryPoint. \r
-#\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
-# \r
-# This program and the accompanying materials \r
-# are licensed and made available under the terms and conditions of the BSD License \r
-# which accompanies this distribution. The full text of the license may be found at \r
-# http://opensource.org/licenses/bsd-license.php \r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-#\r
-#------------------------------------------------------------------------------\r
+//\r
+// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+// \r
+// This program and the accompanying materials \r
+// are licensed and made available under the terms and conditions of the BSD License \r
+// which accompanies this distribution. The full text of the license may be found at \r
+// http://opensource.org/licenses/bsd-license.php \r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+//\r
+//\r
\r
-#include <AsmMacroIoLib.h>\r
-#include <Base.h>\r
-#include <Library/PcdLib.h>\r
-#include <Library/ArmPlatformLib.h>\r
#include <AutoGen.h>\r
+#include <AsmMacroIoLib.h>\r
+#include "SecInternal.h"\r
\r
-#Start of Code section\r
.text\r
.align 3\r
\r
-#make _ModuleEntryPoint as global\r
-GCC_ASM_EXPORT(_ModuleEntryPoint)\r
-\r
-#global functions referenced by this module\r
GCC_ASM_IMPORT(CEntryPoint)\r
-GCC_ASM_IMPORT(ArmPlatformIsMemoryInitialized)\r
-GCC_ASM_IMPORT(ArmPlatformInitializeBootMemory)\r
+GCC_ASM_IMPORT(ArmPlatformSecBootAction)\r
+GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit)\r
GCC_ASM_IMPORT(ArmDisableInterrupts)\r
GCC_ASM_IMPORT(ArmDisableCachesAndMmu)\r
GCC_ASM_IMPORT(ArmWriteVBar)\r
+GCC_ASM_IMPORT(ArmReadMpidr)\r
GCC_ASM_IMPORT(SecVectorTable)\r
+GCC_ASM_IMPORT(ArmCallWFE)\r
+GCC_ASM_EXPORT(_ModuleEntryPoint)\r
\r
-#if (FixedPcdGet32(PcdMPCoreSupport))\r
-GCC_ASM_IMPORT(ArmIsScuEnable)\r
-#endif\r
-\r
-StartupAddr: .word ASM_PFX(CEntryPoint)\r
-SecVectorTableAddr: .word ASM_PFX(SecVectorTable)\r
+StartupAddr: .word ASM_PFX(CEntryPoint)\r
\r
ASM_PFX(_ModuleEntryPoint):\r
- #Set VBAR to the start of the exception vectors in Secure Mode\r
- ldr r0, SecVectorTableAddr\r
- bl ASM_PFX(ArmWriteVBar)\r
+ // First ensure all interrupts are disabled\r
+ bl ASM_PFX(ArmDisableInterrupts)\r
+\r
+ // Ensure that the MMU and caches are off\r
+ bl ASM_PFX(ArmDisableCachesAndMmu)\r
+\r
+ // By default, we are doing a cold boot\r
+ mov r10, #ARM_SEC_COLD_BOOT\r
\r
- # First ensure all interrupts are disabled\r
- bl ASM_PFX(ArmDisableInterrupts)\r
+ // Jump to Platform Specific Boot Action function\r
+ blx ASM_PFX(ArmPlatformSecBootAction)\r
\r
- # Ensure that the MMU and caches are off\r
- bl ASM_PFX(ArmDisableCachesAndMmu)\r
+ // Set VBAR to the start of the exception vectors in Secure Mode\r
+ LoadConstantToReg (ASM_PFX(SecVectorTable), r0)\r
+ bl ASM_PFX(ArmWriteVBar)\r
\r
-_IdentifyCpu: \r
- # Identify CPU ID\r
+_IdentifyCpu:\r
+ // Identify CPU ID\r
bl ASM_PFX(ArmReadMpidr)\r
- and r5, r0, #0xf\r
+ // Get ID of this CPU in Multicore system\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
+ and r5, r0, r1\r
\r
- #get ID of this CPU in Multicore system\r
- cmp r5, #0\r
- # Only the primary core initialize the memory (SMC)\r
+ // Is it the Primary Core ?\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)\r
+ cmp r5, r3\r
+ // Only the primary core initialize the memory (SMC)\r
beq _InitMem\r
\r
-#if (FixedPcdGet32(PcdMPCoreSupport))\r
- # ... The secondary cores wait for SCU to be enabled\r
-_WaitForEnabledScu:\r
- bl ASM_PFX(ArmIsScuEnable)\r
- tst r1, #1\r
- beq _WaitForEnabledScu\r
- b _SetupStack\r
-#endif\r
+_WaitInitMem:\r
+ // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
+ // Otherwise we have to wait the Primary Core to finish the initialization\r
+ cmp r10, #ARM_SEC_COLD_BOOT\r
+ bne _SetupSecondaryCoreStack\r
+\r
+ // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)\r
+ bl ASM_PFX(ArmCallWFE)\r
+ // Now the Init Mem is initialized, we setup the secondary core stacks\r
+ b _SetupSecondaryCoreStack\r
\r
_InitMem:\r
- bl ASM_PFX(ArmPlatformIsMemoryInitialized)\r
- bne _SetupStack\r
+ // Initialize Init Boot Memory\r
+ bl ASM_PFX(ArmPlatformSecBootMemoryInit)\r
\r
- # Initialize Init Memory\r
- bl ASM_PFX(ArmPlatformInitializeBootMemory)\r
-\r
- # Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)\r
- mov r5, #0\r
- \r
-_SetupStack:\r
- # Setup Stack for the 4 CPU cores\r
- #Read Stack Base address from PCD\r
+ // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)\r
+\r
+_SetupPrimaryCoreStack:\r
+ // Get the top of the primary stacks (and the base of the secondary stacks)\r
LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r
+ add r1, r1, r2\r
\r
- #read Stack size from PCD\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecStackSize), r2)\r
+ LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r2)\r
\r
- #calcuate Stack Pointer reg value using Stack size and CPU ID.\r
- mov r3,r5 @ r3 = core_id\r
- mul r3,r3,r2 @ r3 = core_id * stack_size = offset from the stack base\r
- add r3,r3,r1 @ r3 ldr= stack_base + offset\r
- mov sp, r3\r
- \r
- # move sec startup address into a data register\r
- # ensure we're jumping to FV version of the code (not boot remapped alias)\r
+ // The reserved space for global variable must be 8-bytes aligned for pushing\r
+ // 64-bit variable on the stack\r
+ SetPrimaryStack (r1, r2, r3)\r
+ b _PrepareArguments\r
+\r
+_SetupSecondaryCoreStack:\r
+ // Get the top of the primary stacks (and the base of the secondary stacks)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r
+ add r1, r1, r2\r
+\r
+ // Get the Core Position (ClusterId * 4) + CoreId\r
+ GetCorePositionInStack(r0, r5, r2)\r
+ // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
+ add r0, r0, #1\r
+\r
+ // StackOffset = CorePos * StackSize\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)\r
+ mul r0, r0, r2\r
+ // SP = StackBase + StackOffset\r
+ add sp, r1, r0\r
+\r
+_PrepareArguments:\r
+ // Move sec startup address into a data register\r
+ // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
ldr r3, StartupAddr\r
\r
- # Move the CoreId in r0 to be the first argument of the SEC Entry Point\r
+ // Jump to SEC C code\r
+ // r0 = mp_id\r
+ // r1 = Boot Mode\r
mov r0, r5\r
-\r
- # jump to SEC C code\r
- # r0 = core_id\r
- blx r3\r
-\r
-\r
+ mov r1, r10\r
+ blx r3\r
+ \r
+_NeverReturn:\r
+ b _NeverReturn\r
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