-//
-// Copyright (c) 2011, ARM Limited. All rights reserved.
-//
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//
-
-#include <AutoGen.h>
-#include <AsmMacroIoLib.h>
-#include <Base.h>
-#include <Library/PcdLib.h>
-#include <Library/ArmPlatformLib.h>
-
- INCLUDE AsmMacroIoLib.inc
-
- IMPORT CEntryPoint
- IMPORT ArmPlatformSecBootAction
- IMPORT ArmPlatformIsMemoryInitialized
- IMPORT ArmPlatformInitializeBootMemory
- IMPORT ArmDisableInterrupts
- IMPORT ArmDisableCachesAndMmu
- IMPORT ArmWriteVBar
- IMPORT ArmReadMpidr
- IMPORT SecVectorTable
- EXPORT _ModuleEntryPoint
-
-#if (FixedPcdGet32(PcdMPCoreSupport))
- IMPORT ArmIsScuEnable
-#endif
-
- PRESERVE8
- AREA SecEntryPoint, CODE, READONLY
-
-StartupAddr DCD CEntryPoint
-
-_ModuleEntryPoint
- // First ensure all interrupts are disabled
- blx ArmDisableInterrupts
-
- // Ensure that the MMU and caches are off
- blx ArmDisableCachesAndMmu
-
- // Jump to Platform Specific Boot Action function
- blx ArmPlatformSecBootAction
-
- // Set VBAR to the start of the exception vectors in Secure Mode
- ldr r0, =SecVectorTable
- blx ArmWriteVBar
-
-_IdentifyCpu
- // Identify CPU ID
- bl ArmReadMpidr
- // Get ID of this CPU in Multicore system
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)
- and r5, r0, r1
-
- // Is it the Primary Core ?
- LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r1)
- cmp r5, r1
- // Only the primary core initialize the memory (SMC)
- beq _InitMem
-
-#if (FixedPcdGet32(PcdMPCoreSupport))
- // ... The secondary cores wait for SCU to be enabled
-_WaitForEnabledScu
- bl ArmIsScuEnable
- tst r1, #1
- beq _WaitForEnabledScu
- b _SetupStack
-#endif
-
-_InitMem
- bl ArmPlatformIsMemoryInitialized
- bne _SetupStack
-
- // Initialize Init Memory
- bl ArmPlatformInitializeBootMemory
-
- // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
- mov r5, #0
-
-_SetupStack
- // Setup Stack for the 4 CPU cores
- //Read Stack Base address from PCD
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
-
- // Read Stack size from PCD
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecStackSize), r2)
-
- // Calcuate Stack Pointer reg value using Stack size and CPU ID.
- mov r3,r5 // r3 = core_id
- mul r3,r3,r2 // r3 = core_id * stack_size = offset from the stack base
- add r3,r3,r1 // r3 = stack_base + offset
- mov sp, r3
-
- // Move sec startup address into a data register
- // ensure we're jumping to FV version of the code (not boot remapped alias)
- ldr r3, StartupAddr
-
- // Jump to SEC C code
- // r0 = mp_id
- mov r0, r5
- blx r3
-
- END
+//\r
+// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+// \r
+// This program and the accompanying materials \r
+// are licensed and made available under the terms and conditions of the BSD License \r
+// which accompanies this distribution. The full text of the license may be found at \r
+// http://opensource.org/licenses/bsd-license.php \r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+//\r
+//\r
+\r
+#include <AutoGen.h>\r
+#include <AsmMacroIoLib.h>\r
+#include "SecInternal.h"\r
+\r
+ INCLUDE AsmMacroIoLib.inc\r
+ \r
+ IMPORT CEntryPoint\r
+ IMPORT ArmPlatformSecBootAction\r
+ IMPORT ArmPlatformSecBootMemoryInit\r
+ IMPORT ArmDisableInterrupts\r
+ IMPORT ArmDisableCachesAndMmu\r
+ IMPORT ArmReadMpidr\r
+ IMPORT ArmCallWFE\r
+ EXPORT _ModuleEntryPoint\r
+\r
+ PRESERVE8\r
+ AREA SecEntryPoint, CODE, READONLY\r
+ \r
+StartupAddr DCD CEntryPoint\r
+\r
+_ModuleEntryPoint FUNCTION\r
+ // First ensure all interrupts are disabled\r
+ blx ArmDisableInterrupts\r
+\r
+ // Ensure that the MMU and caches are off\r
+ blx ArmDisableCachesAndMmu\r
+\r
+ // By default, we are doing a cold boot\r
+ mov r10, #ARM_SEC_COLD_BOOT\r
+\r
+ // Jump to Platform Specific Boot Action function\r
+ blx ArmPlatformSecBootAction\r
+\r
+_IdentifyCpu \r
+ // Identify CPU ID\r
+ bl ArmReadMpidr\r
+ // Get ID of this CPU in Multicore system\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
+ and r5, r0, r1\r
+ \r
+ // Is it the Primary Core ?\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)\r
+ cmp r5, r3\r
+ // Only the primary core initialize the memory (SMC)\r
+ beq _InitMem\r
+ \r
+_WaitInitMem\r
+ // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
+ // Otherwise we have to wait the Primary Core to finish the initialization\r
+ cmp r10, #ARM_SEC_COLD_BOOT\r
+ bne _SetupSecondaryCoreStack\r
+\r
+ // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)\r
+ bl ArmCallWFE\r
+ // Now the Init Mem is initialized, we setup the secondary core stacks\r
+ b _SetupSecondaryCoreStack\r
+ \r
+_InitMem\r
+ // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
+ cmp r10, #ARM_SEC_COLD_BOOT\r
+ bne _SetupPrimaryCoreStack\r
+\r
+ // Initialize Init Boot Memory\r
+ bl ArmPlatformSecBootMemoryInit\r
+ \r
+ // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)\r
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)\r
+\r
+_SetupPrimaryCoreStack\r
+ // Get the top of the primary stacks (and the base of the secondary stacks)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r
+ add r1, r1, r2\r
+\r
+ LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r2)\r
+\r
+ // The reserved space for global variable must be 8-bytes aligned for pushing\r
+ // 64-bit variable on the stack\r
+ SetPrimaryStack (r1, r2, r3)\r
+ b _PrepareArguments\r
+\r
+_SetupSecondaryCoreStack\r
+ // Get the top of the primary stacks (and the base of the secondary stacks)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r
+ add r1, r1, r2\r
+\r
+ // Get the Core Position (ClusterId * 4) + CoreId\r
+ GetCorePositionFromMpId(r0, r5, r2)\r
+ // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
+ add r0, r0, #1\r
+\r
+ // StackOffset = CorePos * StackSize\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)\r
+ mul r0, r0, r2\r
+ // SP = StackBase + StackOffset\r
+ add sp, r1, r0\r
+\r
+_PrepareArguments\r
+ // Move sec startup address into a data register\r
+ // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
+ ldr r3, StartupAddr\r
+ \r
+ // Jump to SEC C code\r
+ // r0 = mp_id\r
+ // r1 = Boot Mode\r
+ mov r0, r5\r
+ mov r1, r10\r
+ blx r3\r
+ ENDFUNC\r
+ \r
+_NeverReturn\r
+ b _NeverReturn\r
+ END\r
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