ArmPlatformPkg/ArmPlatformLib: Introduce ArmPlatformSecBootAction function

[mirror_edk2.git] / ArmPlatformPkg / Sec / SecEntryPoint.asm

diff --git a/ArmPlatformPkg/Sec/SecEntryPoint.asm b/ArmPlatformPkg/Sec/SecEntryPoint.asm
index 794a8c02d165f0673f0a70d10863ee978e0d49d5..472abde7f2655d2cdb7a1953ad3bfd4aebb860a5 100644 (file)
--- a/ArmPlatformPkg/Sec/SecEntryPoint.asm
+++ b/ArmPlatformPkg/Sec/SecEntryPoint.asm
@@ -20,6 +20,7 @@
   INCLUDE AsmMacroIoLib.inc
   
   IMPORT  CEntryPoint
+  IMPORT  ArmPlatformSecBootAction
   IMPORT  ArmPlatformIsMemoryInitialized
   IMPORT  ArmPlatformInitializeBootMemory
   IMPORT  ArmDisableInterrupts
@@ -39,23 +40,29 @@
 StartupAddr        DCD      CEntryPoint
 
 _ModuleEntryPoint
-  //Set VBAR to the start of the exception vectors in Secure Mode
-  ldr   r0, =SecVectorTable
-  blx   ArmWriteVBar
-
   // First ensure all interrupts are disabled
   blx   ArmDisableInterrupts
 
   // Ensure that the MMU and caches are off
   blx   ArmDisableCachesAndMmu
 
+  // Jump to Platform Specific Boot Action function
+  blx   ArmPlatformSecBootAction
+
+  // Set VBAR to the start of the exception vectors in Secure Mode
+  ldr   r0, =SecVectorTable
+  blx   ArmWriteVBar
+
 _IdentifyCpu 
   // Identify CPU ID
   bl    ArmReadMpidr
-  and   r5, r0, #0xf
+  // Get ID of this CPU in Multicore system
+  LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)
+  and   r5, r0, r1
   
-  //get ID of this CPU in Multicore system
-  cmp   r5, #0
+  // Is it the Primary Core ?
+  LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r1)
+  cmp   r5, r1
   // Only the primary core initialize the memory (SMC)
   beq   _InitMem
   
@@ -97,7 +104,7 @@ _SetupStack
   ldr   r3, StartupAddr
   
   // Jump to SEC C code
-  //    r0 = core_id
+  //    r0 = mp_id
   mov   r0, r5
   blx   r3