--- /dev/null
+#/** @file\r
+#\r
+# Copyright (c) 2014, Linaro Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#**/\r
+\r
+[Defines]\r
+ DEC_SPECIFICATION = 0x00010005\r
+ PACKAGE_NAME = ArmVirtPkg\r
+ PACKAGE_GUID = A0B31216-508E-4025-BEAB-56D836C66F0A\r
+ PACKAGE_VERSION = 0.1\r
+\r
+################################################################################\r
+#\r
+# Include Section - list of Include Paths that are provided by this package.\r
+# Comments are used for Keywords and Module Types.\r
+#\r
+# Supported Module Types:\r
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
+#\r
+################################################################################\r
+[Includes.common]\r
+ Include # Root include for the package\r
+\r
+[Guids.common]\r
+ gArmVirtTokenSpaceGuid = { 0x0B6F5CA7, 0x4F53, 0x445A, { 0xB7, 0x6E, 0x2E, 0x36, 0x5B, 0x80, 0x63, 0x66 } }\r
+ gEarlyPL011BaseAddressGuid = { 0xB199DEA9, 0xFD5C, 0x4A84, { 0x80, 0x82, 0x2F, 0x41, 0x70, 0x78, 0x03, 0x05 } }\r
+\r
+[PcdsFixedAtBuild, PcdsPatchableInModule]\r
+ #\r
+ # This is the physical address where the device tree is expected to be stored\r
+ # upon first entry into UEFI. This needs to be a FixedAtBuild PCD, so that we\r
+ # can do a first pass over the device tree in the SEC phase to discover the\r
+ # UART base address.\r
+ #\r
+ gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x0|UINT64|0x00000001\r
+\r
+ #\r
+ # Padding in bytes to add to the device tree allocation, so that the DTB can\r
+ # be modified in place (default: 256 bytes)\r
+ #\r
+ gArmVirtTokenSpaceGuid.PcdDeviceTreeAllocationPadding|256|UINT32|0x00000002\r
+\r
+[PcdsDynamic, PcdsFixedAtBuild]\r
+ #\r
+ # ARM PSCI function invocations can be done either through hypervisor\r
+ # calls (HVC) or secure monitor calls (SMC).\r
+ # PcdArmPsciMethod == 1 : use HVC\r
+ # PcdArmPsciMethod == 2 : use SMC\r
+ #\r
+ gArmVirtTokenSpaceGuid.PcdArmPsciMethod|0|UINT32|0x00000003\r
+\r
+ gArmVirtTokenSpaceGuid.PcdFwCfgSelectorAddress|0x0|UINT64|0x00000004\r
+ gArmVirtTokenSpaceGuid.PcdFwCfgDataAddress|0x0|UINT64|0x00000005\r
+\r
+[PcdsFeatureFlag]\r
+ #\r
+ # "Map PCI MMIO as Cached"\r
+ #\r
+ # Due to the way Stage1 and Stage2 mappings are combined on Aarch64, and\r
+ # because KVM -- for the time being -- does not try to interfere with the\r
+ # Stage1 mappings, we must not set EFI_MEMORY_UC for emulated PCI MMIO\r
+ # regions.\r
+ #\r
+ # EFI_MEMORY_UC is mapped to Device-nGnRnE, and that Stage1 attribute would\r
+ # direct guest writes to host DRAM immediately, bypassing the cache\r
+ # regardless of Stage2 attributes. However, QEMU's reads of the same range\r
+ # can easily be served from the (stale) CPU cache.\r
+ #\r
+ # Setting this PCD to TRUE will use EFI_MEMORY_WB for mapping PCI MMIO\r
+ # regions, which ensures that guest writes to such regions go through the CPU\r
+ # cache. Strictly speaking this is wrong, but it is needed as a temporary\r
+ # workaround for emulated PCI devices. Setting the PCD to FALSE results in\r
+ # the theoretically correct EFI_MEMORY_UC mapping, and should be the long\r
+ # term choice, especially with assigned devices.\r
+ #\r
+ # The default is to turn off the kludge; DSC's can selectively enable it.\r
+ #\r
+ gArmVirtTokenSpaceGuid.PcdKludgeMapPciMmioAsCached|FALSE|BOOLEAN|0x00000006\r
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