#\r
gArmVirtTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x65, 0x60, 0xA6, 0xDF, 0x19, 0xB4, 0xD3, 0x11, 0x9A, 0x2D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}|VOID*|0x00000007\r
\r
-[PcdsDynamic, PcdsFixedAtBuild]\r
- #\r
- # ARM PSCI function invocations can be done either through hypervisor\r
- # calls (HVC) or secure monitor calls (SMC).\r
- # PcdArmPsciMethod == 1 : use HVC\r
- # PcdArmPsciMethod == 2 : use SMC\r
- #\r
- gArmVirtTokenSpaceGuid.PcdArmPsciMethod|0|UINT32|0x00000003\r
-\r
- gArmVirtTokenSpaceGuid.PcdFwCfgSelectorAddress|0x0|UINT64|0x00000004\r
- gArmVirtTokenSpaceGuid.PcdFwCfgDataAddress|0x0|UINT64|0x00000005\r
- gArmVirtTokenSpaceGuid.PcdFwCfgDmaAddress|0x0|UINT64|0x00000009\r
-\r
[PcdsFeatureFlag]\r
- #\r
- # "Map PCI MMIO as Cached"\r
- #\r
- # Due to the way Stage1 and Stage2 mappings are combined on Aarch64, and\r
- # because KVM -- for the time being -- does not try to interfere with the\r
- # Stage1 mappings, we must not set EFI_MEMORY_UC for emulated PCI MMIO\r
- # regions.\r
- #\r
- # EFI_MEMORY_UC is mapped to Device-nGnRnE, and that Stage1 attribute would\r
- # direct guest writes to host DRAM immediately, bypassing the cache\r
- # regardless of Stage2 attributes. However, QEMU's reads of the same range\r
- # can easily be served from the (stale) CPU cache.\r
- #\r
- # Setting this PCD to TRUE will use EFI_MEMORY_WB for mapping PCI MMIO\r
- # regions, which ensures that guest writes to such regions go through the CPU\r
- # cache. Strictly speaking this is wrong, but it is needed as a temporary\r
- # workaround for emulated PCI devices. Setting the PCD to FALSE results in\r
- # the theoretically correct EFI_MEMORY_UC mapping, and should be the long\r
- # term choice, especially with assigned devices.\r
- #\r
- # The default is to turn off the kludge; DSC's can selectively enable it.\r
- #\r
- gArmVirtTokenSpaceGuid.PcdKludgeMapPciMmioAsCached|FALSE|BOOLEAN|0x00000006\r
-\r
#\r
# Pure ACPI boot\r
#\r
projects / mirror_edk2.git / blobdiff